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Part: 82C50A
Category:
Communication
-> UARTs
Description: CMOS Asynchronous Communications Element
Company: Intersil Corporation
Datasheet: Download 82C50A datasheet File size : 1163 kB
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82C50A
D a ta Sheet Ma y 2003 FN2958.2
CMOS Asynchronous
The 82C50A Asynchronous Communication Element (ACE) is a high performance programmable Universal Asynchronous Receiver/Transmitter (UART) and Baud Rate Generator (BRG) on a single chip. Using Intersil's advanced Scaled SAJI IV CMOS Process, the ACE will support data rates from DC to 625K baud (0-10MHz clock). The ACE's receiver circuitry converts start, data, stop, and parity bits into a parallel data word. The transmitter circuitry converts a parallel data word into serial form and appends the start, parity, and stop bits. The word length is programmable to 5, 6, 7, or 8 data bits. Stop bit selection provides a choice of 1,1.5, or 2 stop bits. The Baud Rate Generator divides the clock by a divisor programmable from 1 to 216-1 to provide standard RS232C baud rates when using any one of three industry standard baud rate crystals (1.8432MHz, 2.4576MHz, or 3.072MHz). A programmable buffered clock output (BAUDOUT) provides either a buffered oscillator or 16X (16 times the data rate) baud rate clock for general purpose system use. To meet the system requirements of a CPU interfacing to an asynchronous channel, the modem control signals RTS, CTS, DSR, DTR, RI, DCD are provided. Inputs and outputs have been designed with full TTL/CMOS compatibility in order to facilitate mixed TTL/NMOS/CMOS system design.
Features
· Single Chip UART/BRG · DC to 625K Baud (DC to 10MHz Clock) · Crystal or External Clock Input · On Chip Baud Rate Generator 1 to 65535 Divisor Generates 16X Clock · Prioritized Interrupt Mode · Fully TTL/CMOS Compatible · Microprocessor Bus Oriented Interface · 80C86/80C88 Compatible · Scaled SAJI IV CMOS Process · Low Power - 1mA/MHz Typical · Modem Interface · Line Break Generation and Detection · Loopback and Echo Modes · Doubled Buffered Transmitter and Receiver · Single 5V Supply
Ordering Information
PACKAGE PDIP PLCC TEMPERATURE RANGE (oC) 0 to +70 0 to +70 -40 to +85 625K BAUD CP82C50A-5 CS82C50A-596 IS82C50A-5 PKG. DWG. # E40.6 N44 .65 N44.65
Functional Diagram
CSO CS1 CS2 ADS A0 A1 A2 MR DISTR DISTR 12 13 14 25 28 27 26 35 22 21 MICROPROCESSOR INTERFACE 24 CSOUT 23 DDIS
INTERRUPT 30 INTRPT ENABLE, ID, & CONTROL UART RECEIVER DIVISOR LATCH LINE STATUS AND CONTROL AND BAUD RATE GENERATOR TRA NSMI TTER MODEM MODEM CONTROL 10 9 16 17 11 32 33 34 31 36 37 38 39 SIN RCLK XTAL1 XTAL2 SOUT R TS D TR OUT1 OUT2 C TS DSR DCD RI
15 BAUDOUT
DOSTR 19 DOSTR 18 D0 D1 D2 D3 D4 D5 D6 D7 1 2 3 4 5 6 7 8
MODEM STATUS
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
82C50A Pinout
82C50A (PDIP) TOP VIEW
D0 D1 D2 D3 D4 D5 D6 D7 RCL K SIN SOUT CS0 CS1 CS2 BA UDOUT XTAL1 XTAL2 DOSTR DOSTR GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 VCC 39 RI 38 DCD 37 DSR 36 CTS 35 MR 34 OUT1 33 DTR 32 RTS 31 OUT2 30 INTRPT 29 NC 28 A0 27 A1 26 A2 25 ADS 24 CSOUT 23 DDIS 22 DISTR 21 DISTR
82C50A (PLCC) TOP VIEW
DCD DSR CTS VCC NC D4 D3 D2 D1 D0 RI
6
5
4
3
2
1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
D5 D6 D7 RCLK SIN
NC
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
MR O U T1 D TR R TS O U T2
NC
SOUT CS0 CS1 CS2 BAUDOUT
I N TR P
NC
A0 A1 A2
XTAL1
XTAL2
DOSTR
DOSTR
CSOUT
DISTR
DISTR
DDIS
GND
2
ADS
NC
82C50A Pin Description
SYMBOL DISTR, DISTR PIN NUMBER 22 21 TYPE I I ACT IVE LEVEL H L DESCRIPTION DATA IN STROBE, DATA IN STROBE: DISTR, DISTR are read inputs which cause the 82C50A to output data to the data bus (D0-D7). The data output depends upon the register selected by the address inputs A0, A1, A2. The chip select inputs CS0, CS1, CS2 enable the DISTR, DISTR inputs. Only an active DISTR or DISTR, not both, is used to receive data from the 82C50A during a read operation. If DISTR is used as the read input, DlSTR should be tied high. If DISTR is used as the active read input, DISTR should be tied low. DATA OUT STROBE, DATA OUT STROBE: DOSTR, DOSTR are write inputs which cause data from the data bus (D0-D7) to be input to the 82C50A. The data input depends upon the register selected by the address inputs A0, A1, A2. The chip select inputs CS0, CS1, CS2 enable the DOSTR, DOSTR inputs. Only an active DOSTR or DOSTR, not both, is used to transmit data to the 82C50A during a write operation. If DOSTR is used as the write input, DOSTR should be tied high. If DOSTR is used as the write input, DOSTR should be tied low. DATA BITS 0-7: The Data Bus provides eight, three-state input/output lines for the transfer of data, control and status information between the 82C50A and the CPU. For character formats of less than 8 bits, D7, D6 and D5 are "don't cares" for data write operations and 0 for data read operations. These lines are normally in a high impedance state except during read operations. D0 is the Least Significant Bit (LSB) and is the first serial data bit to be received or transmitted. REGISTER SELECT: The address lines select the internal registers during CPU bus operations. See Table 1. CRYSTAL/CLOCK: Crystal connections for the internal Baud Rate Generator. XTAL1 can also be used as an external clock input, in which case XTAL2 should be left open. SERIAL DATA OUTPUT: Serial data output from the 82C50A transmitter circuitry. A Mark (1) is a logic one (high) and Space (0) is a logic zero (low). SOUT is held in the Mark condition when the transmitter is disabled, MR is true, the Transmitter Register is empty, or when in the Loop Mode. SOUT is not affected by the CTS input. GROUND: Power supply ground connection (VSS). CLEAR TO SEND: The logical state of the CTS pin is reflected in the CTS bit of the (MSR) Modem Status Register (CTS is bit 4 of the MSR, written MSR (4)). A change of state in the CTS pin since the previous reading of the MSR causes the setting of DCTS (MSR(O)) of the Modem Status Register. When CTS pin is ACTIVE (low), the modem is indicating that data on SOUT can be transmitted on the communications link. If CTS pin goes INACTIVE (high), the 82C50A should not be allowed to transmit data out of SOUT. CTS pin does not affect Loop Mode operation. DATA SET READY: The logical state of the DSR pin is reflected in MSR(5) of the Modem Status Register. DDSR (MSR(1)) indicates whether the DSR pin has changed state since the previous reading of the MSR. When the DSR pin is ACTIVE (low), the modem is indicating that it is ready to exchange data with the 82C50A, while the DSR Pin INACTIVE (high) indicates that the modem is not ready for data exchange. The ACTIVE condition indicates only the condition of the local Data Communications Equipment (DCE), and does not imply that a data circuit as been established with remote equipment. DATA TERMINAL READY: The DTR pin can be set (low) by writing a logic 1 to MCR(0), Modem Control Register bit 0. This signal is cleared (high) by writing a logic 0 to the DTR bit (MCR(0)) or whenever a MR ACTIVE (high) is applied to the 82C50A. When ACTIVE (low), DTR pin indicates to the DCE that the 82C50A is ready to receive data. In some instances, DTR pin is used as a power on indicator. The INACTIVE (high) state causes the DCE to disconnect the modem from the telecommunications circuit. REQUEST TO SEND: The RTS signal is an output used to enable the modem. The RTS pin is set low by writing a logic 1 to MCR (1) bit 1 of the Modem Control Register. The RTS pin is reset high by Master Reset. When ACTIVE, the RTS pin indicates to the DCE that the 82C50A has data ready to transmit. In half duplex operations, RTS is used to control the direction of the line. BAUDOUT: This output is a 16X clock out used for the transmitter section (16X = 16 times the data rate). The BAUDOUT clock rate is equal to the reference oscillator frequency divided by the specified divisor in the Baud Rate Generator Divisor Latches DLL and DLM. BAUDOUT may be used by the Receiver section by tying this output to RCLK.
DOSTR, DOSTR
19 18
I I
H L
D 0- D 7
1- 8
I/O
A0, A1, A2 XTAL1, XTAL2 SOUT
28, 27, 26 16 17 11
I I I O O
H
GND CTS
20 36
I
L L
DSR
37
I
L
DTR
33
O
L
RTS
32
O
L
BAUDOUT
15
O
3
82C50A Pin Description
SYMBOL OUT1 PIN NUMBER 34 (Continued) TYPE O ACT IVE LEVEL L DESCRIPTION OUTPUT 1: This is a general purpose output that can be programmed ACTIVE (low) by settingVCR(2) (OUT1) of the Modem Control Register to a high level. The OUT1 pin is set high by Master Reset. The OUT1 pin is INACTIVE (high) during loop mode operation. OUTPUT 2: This is a general purpose output that can be programmed ACTIVE (low) by setting MCR(3) (OUT1) of the Modem Control Register to a high level. The OUT2 pin is set high by Master Reset. The OUT2 signal is INACTIVE (high) during loop mode operation. RING INDICATOR: When low, RI indicates that a telephone ringing signal has been received by the modem or data set. The RI signal is a modem control input whose condition is tested by reading MSR(6) (RI). The Modem Status Register output TERI (MSR(2)) indicates whether the RI input has changed from a Low to High since the previous reading of the MSR. If the interrupt is enabled (IER (3) = 1) and RI changes from a Low to High, an interrupt is generated. The ACTIVE (low) state of RI indicates that the DCE is receiving a ringing signal. RI will appear ACTIVE for approximately the same length of time as the ACTIVE segment of the ringing cycle. The INACTIVE state of RI will occur during the INACTIVE segments not detected by the DCE. This circuit is not disabled by the INACTIVE condition of DTR. DATA CARRIER DETECT: When ACTIVE (low), DCD indicates that the data carrier has been detected by the modem or data set. DCD is a modem input whose condition can be tested by the CPU by reading MSR(7) (DCD) of the Modem Status Register. MSR(3) (DDCD) of the Modem Status Register indicates whether the DCD input has changed since the previous reading of the MSR. DOD has no effect on the receiver. If the DCD changes state with the modem status interrupt enabled, an interrupt is generated. When DCD is ACTIVE (low), the received line signal from the remote terminal is within the limits specified by the DCE manufacturer. The INACTIVE (high) signal indicates that the signal is not within the specified limits, or is not present. MASTER RESET: The MR input forces the 82C50A into an idle mode in which all serial data activities are suspended. The Modem Control Register (MCR) along with its associated outputs are cleared. The Line Status Register (LSR) is cleared except for the THRE and TEMT bits, which are set. The 82C50A remains in an idle state until programmed to resume serial data activities. The MR input is a Schmitt trigger input. See the DC Electrical Characteristics for Schmitt trigger logic input voltage levels. See Table 7 for a summary of Master Reset's effect on 82C50A operation. INTERRUPT REQUEST: The lNTRPT output goes ACTIVE (high) when one of the following interrupts has an ACTIVE (high) condition and is enabled by the Interrupt Enable Register: Receiver Error flag, Received Data Available, Transmitter Holding Register Empty, and Modem Status. The lNTRPT is reset low upon appropriate service or a MR operation. See Figure 1. Interrupt Control Structure. SERIAL DATA INPUT: The SIN input is the serial data input from the communication line or modem to the 82C50A receiver circuits. A mark (1) is high, and a space (0) is low. Data inputs on SIN are disabled when operating in the loop mode. VCC: +5V positive power supply pin. A 0.1µA decoupling capacitor from VCC (pin 40) to GND (pin 20) is recommended. CHIP SELECT: The Chip Select inputs act as enable signals for the write (DOSTR, DOSTR) and read (DlSTR, DlSTR) input signals. The Chip Select inputs are latched by the ADS input. Do Not Connect CHIP SELECT OUT: When ACTIVE (high), this pin indicates that the chip has been selected by active CS0, CS1, and CS2 inputs. No data transfer can be initiated until CSOUT is a logic 1, ACTIVE (high). DRIVER DISABLE: This output is INACTIVE (low) when the CPU is reading data from the 82C50A. An ACTIVE (high) Dells output can be used to disable an external transceiver when the CPU is reading data. ADDRESS STROBE: When ACTIVE (low), ADS latches the Register Select (A0, A1, A2) and Chip Select (CS0, CS1, CS2) inputs. An active ADS is required when the Register Select pins are not stable for the duration of the read or write operation, multiplexed mode. If not required, the ADS input should be tied low, non-multiplexed mode. This input is the 16X Baud Rate Clock for the receiver section of the 82C50A. This input may be provided from the BAUDOUT output or an external clock.
OUT2
31
O
L
RI
39
1
L
DCD
38
I
L
MR
35
1
H
lNTRPT
30
O
H
SIN
10
I
H
VCC CS0, CS1, CS2 NC C S OUT
40 12 ,13, 14 29 24 I I
H H, H, L
O
H
DDIS
23
O
H
ADS
25
I
L
RCLK
9
I
4
82C50A Block Diagram
RECEIVER BUFFER REGISTER (10) RECEIVER SHIFT RECEIVER (9) RC LK SIN
(1 - 8) D7 - D0 (40) +5V GND (20)
DATA BUS BUFFER
POWER SUPPLY
LINE CONTROL REGISTER
RECEIVER TIMING & CONTROL
(28) A0 (27) A1 (26) A2 DIVISOR (12) CS0 (13) CS1 (14) CS2 (25) ADS (35) MR (22) DISTR (21) DISTR (19) DOSTR (18) DOSTR (23) DDIS (24) CSOUT (16) XTAL1 (17) XTAL2 MODEM STATUS REGISTER MODEM CONTROL REGISTER MODEM CONT ROL LOGIC (37) (38) (39) (34) (31) (36) O U T2 CT S DSR DC D RI (33) (32) RT S DT R O U T1 TRAN SMI TTER HOLDING REGISTER TRAN SMI TTER SHIFT REGISTER (11) SOUT SELECT & CONTROL LOGIC LINE STATUS REGISTER TRAN SMI TTER TIMING & CONTROL LATCH (MS) DIVISOR LATCH (LS) BAUD RATE GENERATOR (15) BA UDOUT
SCRATCH REGISTER
INTERRUPT ENABLE REGISTER INTERRUPT CONTROL INTERRUPT IO REGISTER LOGIC (30) I N TR P T
5
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