|
Details, datasheet, quote on part number:AD7520L
| |
| Part: | AD7520L |
| Category: | Data Conversion => DAC (Digital to Analog Converters) |
| Description: | 10-Bit, 12-Bit, Multiplying D/A Converters |
| Company: | Intersil Corporation |
| Datasheet: | Download AD7520L datasheet File size : 392 kB |
| Request For quote: | Find where to buy AD7520L
|
| |
Datasheet text preview:
®
AD7520, AD7521
D a ta Sheet A u g us t 2002 FN3104.4
10-Bit, 12-Bit, Multiplying D/A Converters
The AD7520 and AD7521 are monolithic, high accuracy, low cost 10-bit and 12-bit resolution, multiplying digital-to-analog converters (DAC). Intersil's thin-film on CMOS processing gives up to 10-bit accuracy with TTL/CMOS compatible operation. Digital inputs are fully protected against static discharge by diodes to ground and positive supply. Typical applications include digital/analog interfacing, multiplication and division, programmable power supplies, CRT character generation, digitally controlled gain circuits, integrators and attenuators, etc.
Features
· AD7520, 10-Bit Resolution; 8-Bit Linearity · AD7521, 12-Bit Resolution; 10-Bit Linearity · Low Power Dissipation (Max). . . . . . . . . . . . . . . . . 20mW · Low Nonlinearity Tempco at 2ppm of FSR/oC · Current Settling Time to 0.05% of FSR . . . . . . . . . . 1.0µs · Supply Voltage Range . . . . . . . . . . . . . . . . . ±5V to +15V · TTL/CMOS Compatible · Full Input Static Protection
Ordering Information
PART NUMBER AD752 0JN AD7521LN L INEAR ITY (INL, DNL) 0.2% (8-Bit) 0.05% (10Bit) TEMP. RANGE (oC) 0 to 70 0 to 70 PACKAGE PKG. NO.
16 Ld PDIP E16.3 18 Ld PDIP E18.3
Pinouts
AD7520 (PDIP) TOP VIEW
IOUT1 IOUT2 GND BIT 1 (MSB) BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 1 2 3 4 5 6 7 8 9
AD7521 (PDIP) TOP VIEW
18 RFEEDBACK 17 VREF 16 V+ 15 BIT 12 (LSB) 14 BIT 11 13 BIT 10 12 BIT 9 11 BIT 8 10 BIT 7
IOUT1 1 IOUT2 2 GND 3 BIT 1 (MSB) 4 BIT 2 5 BIT 3 6 BIT 4 7 BIT 5 8
16 RFEEDBACK 15 VREF 14 V+ 13 BIT 10 (LSB) 12 BIT 9 11 BIT 8 10 BIT 7 9 BIT 6
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved
AD7520, AD7521
Absolute Maximum Ratings
Supply Voltage (V+ to GND) . . . . . . . . . . . . . . . . . . . . . . . . . . .+17V VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25V Digital Input Voltage Range . . . . . . . . . . . . . . . . . . . . . . . V+ to GND Output Voltage Compliance . . . . . . . . . . . . . . . . . . . . . -100mV to V+
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) 16 Ld PDIP Package 90 18 Ld PDIP Package 80 JC (oC/W) N/A N/A
Operating Conditions
Temperature Ranges JN, LN Versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC
Maximum Junction Temperature (Plastic Packages) . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. The digital control inputs are zener protected; however, permanent damage may occur on unconnected units under high energy electrostatic fields. Keep unused units in conductive foam at all times. Do not apply voltages higher than VDD or less than GND potential on any terminal except VREF and RFEEDBACK.
1. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
PARAMET ER
V+ = +15V, VREF = +10V, TA = 25oC Unless Otherwise Specified AD7520 TEST CONDITIONS MIN 10 TYP 10 ±0.3 MAX 10 ± 0.2 (8-Bit) ± 0.05 (10-Bit) ±2 ±10 ±200 MIN 12 AD7521 TYP 12 ±0.3 MAX 12 ±0.05 (10-Bit) ±2 ±10 ±200 UNITS Bits % of FSR % of FSR ppm of FSR/oC % of FSR ppm of FSR/oC nA
SYSTEM PERFORMANCE (Note 2) Resolution Nonlinearity J L Nonlinearity Tempco Gain Error Gain Error Tempco Output Leakage Current (Either Output) DYNAMIC CHARACTERISTICS Output Current Settling Time To 0.05% of FSR (All Digital Inputs Low To High And High To Low) (Note 4) (Figure 7) VREF = 20VP-P , 100kHz All Digital Inputs Low (Note 4) (Figure 6) All Digital Inputs High IOUT1 at Ground IOUT1 All Digital Inputs High (Note 4) (Figure 5) I
OUT2 OUT2
(Note 3) (Figure 2) -10V VREF +10V -10V VREF +10V (Figure 2) -10V VREF +10V (Notes 3, 4)
-
Over the Specified Temperature Range
-
-
1. 0
-
-
1. 0
-
µs
Feedthrough Error
-
-
10
-
-
10
mVP-P
REFERENCE INPUT Input Resistance ANALOG OUTPUT Output Capacitance 20 0 75 75 20 0 Equivalent to 10k 200 75 75 200 Equivalent to 10k pF pF pF pF Johnson Noise V V µA 5 10 20 5 10 20 k
IOUT1 All Digital Inputs Low (Note 4) (Figure 5) I Output Noise DIGITAL INPUTS Low State Threshold, VIL High State Threshold, VIH Input Current, IIL, IIH Input Coding Over the Specified Temperature Range VIN = 0V or +15V See Tables 1 and 2 Both Outputs (Note 4) (Figure 4)
2.4 -
0. 8 ±1
2. 4 -
0. 8 ±1
Binary/Offset Binary
2
AD7520, AD7521
Electrical Specifications
PARAMET ER POWER SUPPLY CHARACTERISTICS Power Supply Rejection V+ = 14.5V to 15.5V (Note 3) (Figure 3) ±0.005 ±0.005 % FSR/% V+ V 2 µA mA mW V+ = +15V, VREF = +10V, TA = 25oC Unless Otherwise Specified (Continued) AD7520 TEST CONDITIONS MIN TYP MAX MIN AD7521 TYP MAX UNITS
Power Supply Voltage Range I+ All Digital Inputs at 0V or V+ Excluding Ladder Network All Digital Inputs High or Low Excluding Ladder Network Total Power Dissipation NOTES: 2. Full Scale Range (FSR) is 10V for Unipolar and ±10V for Bipolar modes. 3. Using internal feedback resistor RFEEDBACK . 4. Guaranteed by design, or characterization and not production tested. 5. Accuracy not guaranteed unless outputs at GND potential. 6. Accuracy is tested and guaranteed at V+ = 15V only. Including the Ladder Network -
+5 to +15 ±1 20 2 -
+5 to +15 ±1 20
Functional Diagram
VREF 20k 10k 20k 10k 20k 10k 20k 10k 20k 20k GND SPDT NMOS SWITCHES I OUT2 IOUT1
NOTES:
MSB
BIT 2
BIT 3
Switches shown for Digital Inputs "High". Resistor values are typical.
10k
RFEEDBACK
Pin Descriptions
AD7520 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 AD7521 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 PIN NAME IOUT1 IOUT2 GND Bits 1(MSB) Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 V+ VREF RFEEDBACK DESCRIPTION Current Out summing junction of the R2R ladder network. Current Out virtual ground, return path for the R2R ladder network. Digital Ground. Ground potential for digital side of D/A. Most Significant Digital Data Bit. Digital Bit 2. Digital Bit 3. Digital Bit 4. Digital Bit 5. Digital Bit 6. Digital Bit 7. Digital Bit 8. Digital Bit 9. Digital Bit 10 (AD7521). Least Significant Digital Data Bit (AD7520). Digital Bit 11 (AD7521). Least Significant Digital Data Bit (AD7521). Power Supply +5V to +15V. Voltage Reference Input to set the output range. Supplies the R2R resistor ladder. Feedback resistor used for the current to voltage conversion when using an external Op Amp.
3
AD7520, AD7521 Definition of Terms
Nonlinearity: Error contributed by deviation of the DAC transfer function from a "best straight line" through the actual plot of transfer function. Normally expressed as a percentage of full scale range or in (sub)multiples of 1 LSB. Resolution: It is addressing the smallest distinct analog output change that a D/A converter can produce. It is commonly expressed as the number of converter bits. A converter with resolution of N bits can resolve output changes of 2-N of the full-scale range, e.g., 2-N VREF for a unipolar conversion. Resolution by no means implies linearity. Settling Time: Time required for the output of a DAC to settle to within specified error band around its final value (e.g., 1/2 LSB) for a given digital input change, i.e., all digital inputs LOW to HIGH and HIGH to LOW. Gain Error: The difference between actual and ideal analog output values at full scale range, i.e., all digital inputs at HIGH state. It is expressed as a percentage of full scale range or in (sub)multiples of 1 LSB. Feedthrough Error: Error caused by capacitive coupling from VREF to IOUT1 with all digital inputs LOW. Output Capacitance: Capacitance from IOUT1 and IOUT2 terminals to ground. Output Leakage Current: Current which appears on IOUT1 terminal when all digital inputs are LOW or on IOUT2 terminal when all digital inputs are HIGH. current reference and an operational amplifier are all that is required for most voltage output applications. A simplified equivalent circuit of the DAC is shown in the Functional Diagram. The NMOS SPDT switches steer the ladder leg currents between IOUT1 and IOUT2 buses which must be held either at ground potential. This configuration maintains a constant current in each ladder leg independent of the input code. Converter errors are further reduced by using separate metal interconnections between the major bits and the outputs. Use of high threshold switches reduce offset (leakage) errors to a negligible level. The level shifter circuits are comprised of three inverters with positive feedback from the output of the second to the first, see Figure 1. This configuration results in TTL/CMOS compatible operation over the full military temperature range. With the ladder SPDT switches driven by the level shifter, each switch is binarily weighted for an ON resistance proportional to the respective ladder leg current. This assures a constant voltage drop across each switch, creating equipotential terminations for the 2R ladder resistors and highly accurate leg currents.
V+
13 4 6 TO LADDER 8 9
Detailed Description
The AD7520 and AD7521 are monolithic, multiplying D/A converters. A highly stable thin film R-2R resistor ladder network and NMOS SPDT switches form the basis of the converter circuit, CMOS level shifters permit low power TTL/CMOS compatible operation. An external voltage or
DTL/T TL/ CMOS INPUT
2
5
7 I OUT2 I OUT1
FIGURE 1. CMOS LEVEL SHIFTER AND SWITCH
Test Circuits
BIT 1 (MSB) 10-BIT BINARY COUNTER
The following test circuits apply for the AD7520. Similar circuits are used for the AD7521.
+15V +15V UNGROUNDED SINE WAVE GENERATOR 40Hz 1VP-P 5K 0.01% 5k 0.01%
VREF
RFEEDBACK 4 15 16 IOUT1 1 5 AD7520 HA2600 I BIT 10 + 13 3 2 OUT2 (LSB) GND
10k 0.01% 1M
500k
VREF
+10V BIT 1 (MSB)
HA2600 + VERROR x 100
CLOCK
BIT 1 (MSB) BIT 10 BIT 11 BIT 12
V REF 10k 0.01% 12-BIT REFERENCE DAC
HA2600 + LINEARITY ERROR x 100
BIT 10 (LSB)
14 RFEEDBACK 16 I OUT1 1 5 AD7520 I OUT2 HA2600 13 3 2 + 15 4
GND
FIGURE 2. NONLINEARITY
FIGURE 3. POWER SUPPLY REJECTION
4
AD7520, AD7521 Test Circuits
The following test circuits apply for the AD7520. Similar circuits are used for the AD7521. (Continued)
+11V (ADJUST FOR VOUT = 0V) +15V 1K f = 1kHz BW = 1Hz 15µF 15 4 14 IOUT2 2 100 10k QUAN TECH MODEL 134D 101ALN WAVE VOUT ANALYZER + 1k 0.1µF -50V +15V BIT 1 (MSB) NC +15V
5 AD7520 IOUT1 13 3 1 50k
BIT 10 (LSB)
15 14 4 16 5 AD7520 1 13 3 2
NC 1k 100mVP-P 1MHz
SCOPE
FIGURE 4. NOISE
FIGURE 5. OUTPUT CAPACITANCE
5t: 1% SETTLING (1mV) EXTRAPOLATE 8t: 0.03% SETTLING t = RISE TIME +15V 15 14 4 5 AD7520 1 13 3 2 GND
VREF = 20VP-P 100kHz SINE WAVE BIT 1 (MSB)
+15V +10V VREF
BIT 10 (LSB)
15 14 4 16 5 IOUT1 AD7520 1 IOUT2 13 3 2 GND
BIT 1 (MSB) 3 6 HA2600 2+ +5V 0V DIGITAL INPUT BIT 10 (LSB)
VOUT
+100mV IOUT2 100
SCOPE
FIGURE 6. FEEDTHROUGH ERROR
FIGURE 7. OUTPUT CURRENT SETTLING TIME
Applications
Unipolar Binary Operation
The circuit configuration for operating the AD7520 in unipolar mode is shown in Figure 8. Similar circuits can be used for AD7521. With positive and negative VREF values the circuit is capable of 2-Quadrant multiplication. The Digital Input Code/Analog Output Value table for unipolar mode is given in Table 1.
+15V
TABLE 1. CODE TABLE - UNlPOLAR BINARY OPERATION DIGITAL INPUT 1111111111 1000000001 1000000000 0111111111 0000000001 ANALOG OUTPUT -VREF (1-2-N) -VREF (1/2 + 2-N) -VREF/2 -VREF (1/2-2-N) -VREF (2-N) 0
VREF BIT 1 (MSB)
0000000000 NOTES:
RFEEDBACK IOUT1 IOUT2
DIGITAL INPUT BIT 10 (LSB)
15 14 4 16 5 AD7520 1 13 3 2
1. LSB = 2-N VREF.
6 + VOUT
2. N = 8 for 7520 N = 10 for 7521.
Zero Offset Adjustment
1. Connect all digital inputs to GND. 2. Adjust the offset zero adjust trimpot of the output operational amplifier for 0V at VOUT.
GND
FIGURE 8. UNIPOLAR BINARY OPERATION (2-QUADRANT MULTIPLICATION)
Gain Adjustment
1. Connect all digital inputs to V+. 2. Monitor VOUT for a -VREF (1-2-N) reading. (N = 8 for AD7520 and N = 10 for AD7521).
5
|
|
