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Details, datasheet, quote on part number:AD7520UD883B
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Datasheet text preview:
AD7520, AD7530, AD7521, AD7531
August 1997
10-Bit, 12-Bit, Multiplying D/A Converters
Description
The AD7520/AD7530 and AD7521/AD7531 are monolithic, high accuracy, low cost 10-bit and 12-bit resolution, multiplying digital-to-analog converters (DAC). Intersil' thin-film on CMOS processing gives up to 10-bit accuracy with TTL/CMOS compatible operation. Digital inputs are fully protected against static discharge by diodes to ground and positive supply. Typical applications include digital/analog interfacing, multiplication and division, programmable power supplies, CRT character generation, digitally controlled gain circuits, integrators and attenuators, etc. The AD7530 and AD7531 are identical to the AD7520 and AD7521, respectively, with the exception of output leakage current and feedthrough specifications.
Features
· AD7520/AD7530, 10-Bit Resolution; 8-Bit, 9-Bit and 10-Bit Linearity · AD7521/AD7531, 12-Bit Resolution; 8-Bit, 9-Bit and 10-Bit Linearity · Low Power Dissipation (Max) . . . . . . . . . . . . . . . .20mW · Low Nonlinearity Tempco at 2ppm of FSR/oC · Current Settling Time to 0.05% of FSR . . . . . . . . 1.0µs · Supply Voltage Range . . . . . . . . . . . . . . . . ±5V to +15V · TTL/CMOS Compatible · Full Input Static Protection · /883B Processed Versions Available
Ordering Information
PART NUMBER AD7520JN, AD7530JN AD7520KN, AD7530KN AD7521JN, AD7531JN AD7521KN, AD7531KN AD7520LN, AD7530LN AD7521LN, AD7531LN AD7520JD AD7520KD AD7520LD AD7520SD, AD7520SD/883B AD7520UD, AD7520UD/883B LINEARITY (INL, DNL) 0.2% (8-Bit) 0.1% (9-Bit) 0.2% (8-Bit) 0.1% (9-Bit) 0.05% (10-Bit) 0.05% (10-Bit) 0.2% (8-Bit) 0.1% (9-Bit) 0.05% (10-Bit) 0.2% (8-Bit) 0.05% (10-Bit) TEMP. RANGE (oC) 0 to 70 0 to 70 0 to 70 0 to 70 -40 to 85 -40 to 85 -25 to 85 -25 to 85 -25 to 85 -55 to 125 -55 to 125 PACKAGE 16 Ld PDIP 16 Ld PDIP 18 Ld PDIP 18 Ld PDIP 16 Ld PDIP 18 Ld PDIP 16 Ld CERDIP 16 Ld CERDIP 16 Ld CERDIP 16 Ld CERDIP 16 Ld CERDIP PKG. NO. E16.3 E16.3 E18.3 E18.3 E16.3 E18.3 F16.3 F16.3 F16.3 F16.3 F16.3
Pinouts
AD7520, AD7530 (CERDIP, PDIP) TOP VIEW
IOUT1 1 IOUT2 2 GND 3 BIT 1 (MSB) 4 BIT 2 5 BIT 3 6 BIT 4 7 BIT 5 8 16 RFEEDBACK 15 VREF 14 V+ 13 BIT 10 (LSB) 12 BIT 9 11 BIT 8 10 BIT 7 9 BIT 6
AD7521, AD7531 (PDIP) TOP VIEW
IOUT1 1 IOUT2 2 GND BIT 1 (MSB) BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 3 4 5 6 7 8 9 18 RFEEDBACK 17 VREF 16 V+ 15 BIT 12 (LSB) 14 BIT 11 13 BIT 10 12 BIT 9 11 BIT 8 10 BIT 7
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
File Number
3104.1
10-7
AD7520, AD7530, AD7521, AD7531
Absolute Maximum Ratings
Supply Voltage (V+ to GND). . . . . . . . . . . . . . . . . . . . . . . . . . . +17V VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25V Digital Input Voltage Range . . . . . . . . . . . . . . . . . . . . . . . V+ to GND Output Voltage Compliance . . . . . . . . . . . . . . . . . . . . -100mV to V+
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) JC (oC/W) 16 Ld PDIP Package . . . . . . . . . . . . . . . . 100 N/A 18 Ld PDIP Package . . . . . . . . . . . . . . . . 90 N/A CERDIP Package . . . . . . . . . . . . . . . . . . 75 20 Maximum Junction Temperature (Hermetic Package) . . . . . . . . 175oC Maximum Junction Temperature (Plastic Packages) . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
Operating Conditions
Temperature Ranges JN, KN, LN Versions . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to 70oC JD, KD, LD Versions . . . . . . . . . . . . . . . . . . . . . . . . -25oC to 85oC SD, UD Versions . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. The digital control inputs are zener protected; however, permanent damage may occur on unconnected units under high energy electrostatic fields. Keep unused units in conductive foam at all times. Do not apply voltages higher than VDD or less than GND potential on any terminal except VREF and RFEEDBACK.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
V+ = +15V, VREF = +10V, TA = 25oC Unless Otherwise Specified AD7520/AD7530 AD7521/AD7531 MIN TYP MAX UNITS
PARAMETER SYSTEM PERFORMANCE (Note 2) Resolution Nonlinearity J, S K L, U
TEST CONDITIONS
MIN
TYP
MAX
10 S Over -55oC to 125oC (Notes 2, 5) (Figure 3) T Over -55oC to 125oC (Figure 2) -10V VREF +10V U Over -55oC to 125oC (Figure 2) -10V VREF +10V (Notes 3, 4) -
10 -
10 ±0.2 (8-Bit) ±0.1 (9-Bit) ±0.05 (10-Bit) ±2 ±10 ±200 (±300)
12 -
12 -
12 ±0.2 (8-Bit) ±0.1 (9-Bit) ±0.05 (10-Bit) ±2 ±10 ±200 (±300)
Bits % of FSR % of FSR % of FSR ppm of FSR/oC % of FSR ppm of FSR/oC nA
Nonlinearity Tempco Gain Error Gain Error Tempco Output Leakage Current (Either Output) DYNAMIC CHARACTERISTICS Output Current Settling Time
-
±0.3 -
-
±0.3 -
Over the Specified Temperature Range
-
To 0.05% of FSR (All Digital Inputs Low To High And High To Low) (Note 4) (Figure 7) VREF = 20VP-P , 10kHz (50kHz) All Digital Inputs Low (Note 4) (Figure 6)
-
1.0
-
-
1.0
-
µs
Feedthrough Error
-
-
10
-
-
10
mVP-P
REFERENCE INPUT Input Resistance ANALOG OUTPUT Output Capacitance IOUT1 All Digital Inputs High (Note 4) (Figure 5) IOUT2 IOUT1 All Digital Inputs Low (Note 4) (Figure 5) IOUT2 200 75 75 200 200 75 75 200 pF pF pF pF All Digital Inputs High IOUT1 at Ground 5 10 20 5 10 20 k
10-8
AD7520, AD7530, AD7521, AD7531
Electrical Specifications
V+ = +15V, VREF = +10V, TA = 25oC Unless Otherwise Specified (Continued) AD7520/AD7530 PARAMETER Output Noise DIGITAL INPUTS Low State Threshold, VIL High State Threshold, VIH Input Current, IIL, IIH Input Coding See Tables 1 and 2 ±0.005 +5 to +15 All Digital Inputs at 0V or V+ Excluding Ladder Network All Digital Inputs High or Low Excluding Ladder Network Total Power Dissipation NOTES: 2. Full scale range (FSR) is 10V for Unipolar and ±10V for Bipolar modes. 3. Using internal feedback resistor RFEEDBACK . 4. Guaranteed by design, or characterization and not production tested. 5. Accuracy not guaranteed unless outputs at GND potential. 6. Accuracy is tested and guaranteed at V+ = 15V only. Including the Ladder Network ±1 20 2 Over the Specified Temperature Range VIN = 0V or +15V 2.4 0.8 ±1 2.4 0.8 ±1 V V µA TEST CONDITIONS Both Outputs (Note 4) (Figure 4) MIN TYP Equivalent to 10k MAX MIN AD7521/AD7531 TYP Equivalent to 10k MAX UNITS Johnson Noise
Binary/Offset Binary ±0.005 +5 to +15 ±1 20 2 -
POWER SUPPLY CHARACTERISTICS Power Supply Rejection Power Supply Voltage Range I+ V+ = 14.5V to 15.5V (Note 3) (Figure 3) % FSR/ % V+ V µA mA mW
Functional Diagram
VREF
10k
10k
10k
10k
20k
20k
20k
20k
20k
20k GND
SPDT NMOS SWITCHES
IOUT2 IOUT1 10k MSB BIT 2 BIT 3 RFEEDBACK
NOTES: Switches shown for Digital Inputs "High". Resistor values are typical.
10-9
AD7520, AD7530, AD7521, AD7531 Pin Descriptions
AD7520/30 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 AD7521/31 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 PIN NAME IOUT1 IOUT2 GND Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 V+ VREF DESCRIPTION Current Out summing junction of the R2R ladder network. Current Out virtual ground, return path for the R2R ladder network. Digital Ground. Ground potential for digital side of D/A. Digital Bit 2. Digital Bit 3. Digital Bit 4. Digital Bit 5. Digital Bit 6. Digital Bit 7. Digital Bit 8. Digital Bit 9. Digital Bit 10 (AD7521/31). Least Significant Digital Data Bit (AD7520/30). Digital Bit 11 (AD7521/31). Least Significant Digital Data Bit (AD7521/31). Power Supply +5V to +15V. Voltage Reference Input to set the output range. Supplies the R2R resistor ladder.
Bits 1(MSB) Most Significant Digital Data Bit.
RFEEDBACK Feedback resistor used for the current to voltage conversion when using an external Op Amp.
Definition of Terms
Nonlinearity: Error contributed by deviation of the DAC transfer function from a "best straight line" through the actual plot of transfer function. Normally expressed as a percentage of full scale range or in (sub)multiples of 1 LSB. Resolution: It is addressing the smallest distinct analog output change that a D/A converter can produce. It is commonly expressed as the number of converter bits. A converter with resolution of n bits can resolve output changes of 2-N of the full-scale range, e.g., 2-N VREF for a unipolar conversion. Resolution by no means implies linearity. Settling Time: Time required for the output of a DAC to settle to within specified error band around its final value (e.g., 1/ LSB) for a given digital input change, i.e., all digital inputs 2 LOW to HIGH and HIGH to LOW. Gain Error: The difference between actual and ideal analog output values at full scale range, i.e., all digital inputs at HIGH state. It is expressed as a percentage of full scale range or in (sub)multiples of 1 LSB. Feedthrough Error: Error caused by capacitive coupling from VREF to IOUT1 with all digital inputs LOW. Output Capacitance: Capacitance from IOUT1 and IOUT2 terminals to ground. Output Leakage Current: Current which appears on IOUT1 terminal when all digital inputs are LOW or on IOUT2 terminal when all digital inputs are HIGH. or current reference and an operational amplifier are all that is required for most voltage output applications. A simplified equivalent circuit of the DAC is shown in the Functional Diagram. The NMOS SPDT switches steer the ladder leg currents between IOUT1 and IOUT2 buses which must be held either at ground potential. This configuration maintains a constant current in each ladder leg independent of the input code. Conver ter errors are further reduced by using separate metal interconnections between the major bits and the outputs. Use of high threshold switches reduce offset (leakage) errors to a negligible level. The level shifter circuits are comprised of three inverters with positive feedback from the output of the second to the first, see Figure 1. This configuration results in TTL/CMOS compatible operation over the full military temperature range. With the ladder SPDT switches driven by the level shifter, each switch is binarily weighted for an ON resistance proportional to the respective ladder leg current. This assures a constant voltage drop across each switch, creating equipotential terminations for the 2R ladder resistors and highly accurate leg currents.
V+ 13 4 6 TO LADDER
8
9
Detailed Description
The AD7520, AD7530, AD7521 and AD7531 are monolithic, multiplying D/A converters. A highly stable thin film R-2R resistor ladder network and NMOS SPDT switches form the basis of the converter circuit, CMOS level shifters permit low power TTL/CMOS compatible operation. An external voltage
DTL/TTL/ CMOS INPUT 2 5 7 IOUT2 IOUT1
FIGURE 1. CMOS SWITCH
10-10
AD7520, AD7530, AD7521, AD7531 Test Circuits
The following test circuits apply for the AD7520. Similar circuits are used for the AD7530, AD7521 and AD7531.
VREF BIT 1 (MSB) 10-BIT BINARY COUNTER
+15V
RFEEDBACK 4 15 16 IOUT1 1 5 AD7520 HA2600 I BIT 10 13 3 2 OUT2 + (LSB) GND BIT 1 (LSB) VREF 10k 0.01% 12-BIT REFERENCE DAC
+15V
10k 0.01% 1M
VREF
+10V BIT 1 (MSB)
UNGROUNDED SINE WAVE GENERATOR 400Hz 1VP-P 5K 0.01% 5k 0.01%
500k
15 14 RFEEDBACK 4 16 I OUT1 1 5 AD7520 I OUT2 HA2600 13 3 2 + HA2600 +
CLOCK
HA2600 + LINEARITY ERROR X 100
BIT 10 BIT 11 BIT 12
BIT 10 (LSB)
GND
FIGURE 2. NONLINEARITY
FIGURE 3. POWER SUPPLY REJECTION
+11V (ADJUST FOR VOUT = 0V) +15V 1K f = 1kHz BW = 1Hz 15µF 15 14 IOUT2 4 2 5 AD7520 IOUT1 13 3 1 100 10k QUAN TECH MODEL 134D 101ALN WAVE VOUT ANALYZER + +15V BIT 1 (MSB) 15 14 4 16 5 AD7520 1 13 3 2 NC +15V
-
NC 1k 100mVP-P 1MHz SCOPE
50k
1k 50V 0.1µF BIT 10 (LSB)
FIGURE 4. NOISE
FIGURE 5. OUTPUT CAPACITANCE
VREF = 20VP-P 100kHz SINE WAVE BIT 1 (MSB)
+15V -10V 15 14 4 16 5 AD7520 1 13 3 2 VREF
5t: 1% SETTLING (1mV) EXTRAPOLATE 8t: 0.03% SETTLING t = RISE TIME +15V
BIT 1 (MSB) IOUT1 IOUT2 3
VOUT
+5V 0V DIGITAL INPUT BIT 10 (LSB)
BIT 10 (LSB)
6 HA2600 2+
15 14 4 5 AD7520 1 13 3 2 GND
+100mV IOUT2 100
SCOPE
GND
FIGURE 6. FEEDTHROUGH ERROR
FIGURE 7. OUTPUT CURRENT SETTLING TIME
10-11
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