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Details, datasheet, quote on part number:AD7523
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| Part: | AD7523 |
| Category: | Data Conversion => DAC (Digital to Analog Converters) => <10 bit |
| Description: | 8-Bit, Multiplying D/A Converters |
| Company: | Intersil Corporation |
| Datasheet: | Download AD7523 datasheet File size : 255 kB |
| Request For quote: | Find where to buy AD7523
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Datasheet text preview:
TM
AD7523, AD7533
D a t a Sheet J an ua ry 2001 F N31 05. 2
8-Bit, 10-Bit Multiplying D/A Converters
The AD7523 and AD7533 are monolithic, low cost, high performance, 8-bit and 10-bit accurate, multiplying digital-toanalog converter (DAC), in a 16 pin DIP. Intersil's thin film resistors on CMOS circuitry provide 10-bit resolution (8-bit accuracy), with TTL/CMOS compatible operation. The AD7523 and AD7533's accurate four quadrant multiplication, full input protection from damage due to static discharge by clamps to V+ and GND, and very low power dissipation make them very versatile converters. Low noise audio gain controls, motor speed controls, digitally controlled gain and digital attenuators are a few of the wide range of applications of the AD7523 and AD7533.
Features
· 8-Bit Linearity · Low Gain and Linearity Temperature Coefficients · Full Temperature Range Operation · Static Discharge Input Protection · TTL/CM OS Compatible · Supply Range. . . . . . . . . . . . . . . . . . . . . . . . . +5V to +15V · Fast Settling Time at 25oC . . . . . . . . . . . . . . 150ns (Max) · Four Quadrant Multiplication · AD7533 Direct AD7520 Equivalent
Pinout
AD7523, AD7533 (PDIP) TOP VIEW
IOUT1 IOUT2 1 2 16 RFEEDBACK 15 VREF IN 14 V+ NC/BIT 10 13 (NOTE) 12 NC/BIT 9 (NOTE) 11 BIT 8 10 BIT 7 9 BIT 6
Functional Block Diagram
VREF IN (15) 20k 20 k 20 k 20 k 20k 20 k (3 ) SPDT NMOS SWITCHES 10k MSB (4) BIT 2 (5) BIT 3 (6) RFEEDBACK (1 6) 1 0k 10k 10k 10k
G ND 3 BIT 1 (MSB) 4
BIT 2 5 BIT 3 6 BIT 4 7 BIT 5 8
IOUT2 (2) IOUT1 (1)
NOTE: NC for AD7523 only.
NOTE: S witches shown for digital inputs "High"
Ordering Information
PART NUMBER AD7523JN AD7533JN NUMBER OF BITS 8 10 LINEARITY (INL, DNL) 0.2% (8-Bit) 0.2% (8-Bit) TEMP. RANGE (oC) 0 to 70 0 to 70 PACKAGE 16 Ld PDIP 16 Ld PDIP PKG. NO. E16.3 E16.3
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved
AD7523, AD7533
Absolute Maximum Ratings
Supply Voltage (V+ to GND) . . . . . . . . . . . . . . . . . . . . . . . . . . .+17V VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25V Digital Input Voltage Range . . . . . . . . . . . . . . . . . . . . . . . V+ to GND Output Voltage Compliance . . . . . . . . . . . . . . . . . . . . . -100mV to V+
Thermal Information
Thermal Resistance (Typical, Note 1) JA ( oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC Maximum Storage Temperature . . . . . . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
Operating Conditions
Temper ature Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
V+ = +15V, VREF = +10V, VOUT1 = VOUT2 = 0V, Unless Otherwise Specified AD7523 TA 25oC M AX TA MIN-MAX MIN M AX TA MIN AD7533 25oC M AX TA MIN-MAX MIN M AX UN ITS
PARAMETER SY STE M PERFORMANCE Resolution Nonlinearity
TEST CONDITIONS
MIN
8 -10V VREF +10V, VOUT1 = VOUT2 = 0V (Notes 2, 3, 6) -
±0.2
8 -
±0.2
10 -
±0.2
10 -
±0.2
Bits % of FSR
Monotonicity Gain Error Nonlinearity Tempco Gain Error Tempco Output Leakage Current (E ither Output) DY NAMIC CHARACTERISTICS Power Supply Rejection V+ = 14.0V to 15.0V (Note 3) VOUT1 = VOUT2 = 0 All Digital Inputs High (Note 3) -10V VREF + 10V (Notes 3, 4) -
Guaranteed ±1.5 ±2 ±10 ±50 ±1.8 ±2 ±10 ±200 -
Guaranteed ±1.4 ±2 ±10 ±50 ±1.8 ±2 ±10 ±200 % of FSR ppm of FSR/oC ppm of FSR/oC nA
±0.02
-
±0.03
-
±0.005
-
±0.008
% of FSR/% of V+ ns LSB
Output Current Settling Time Feedthrough Error
To 0.2% of FSR, RL = 100 (Note 4) VREF = 20VP-P , 200kHz Sine Wave, All Digital Inputs Low (Note 4)
-
150 ±1/2
-
200 ±1
-
600 ±0.05
-
800 ±0.1
RE FERENCE INPUTS Input Resistance (Pin 15) All Digital Inputs High IOUT1 at Ground (Note 4) 5 20 -500 5 20 -500 5 20 -300 5 20 -300 k k ppm/C
Temperature Coefficient
2
AD7523, AD7533
Electrical Specifications
V+ = +15V, VREF = +10V, VOUT1 = VOUT2 = 0V, Unless Otherwise Specified (Continued) AD7523 TA PARAMETER ANALOG OUTPUT Output Capacitance COUT1 All Digital Inputs High (Note 4) COUT2 COUT1 All Digital Inputs Low (Note 4) COUT2 DIGITAL INPUTS Low State Threshold, V IL High State Threshold, VIH Input Current (Low or High), IIL, IIH VIN = 0V or + 15V Input Coding Input Capacitance See Tables 1 through 3 (Note 4) 2,4 0.8 ±1 2,4 0.8 ±1 2.4 0.8 ±1 2.4 0.8 ±1 V V µA 100 30 30 100 100 30 30 100 100 35 35 100 100 35 35 100 pF pF pF pF TE ST CONDITIONS MIN 25oC M AX TA MIN-MAX MIN M AX TA MIN AD7533 25oC M AX TA MIN-MAX MIN M AX UN ITS
Binary/Offset Binary 4 4 -
Binar y/Offset Binary 4 4 pF
POWER SUPPLY CHARACTERISTICS Power Supply Voltage Range I+ (Note 6) All Digital Inputs High or Low (Excluding Ladder Network) +5 to +16 2 2.5 +5 to +16 2 2.5 V mA
NOTES : 2. Full Scale Range (FSR) is 10V for unipolar and ±10V for bipolar modes. 3. Using internal feedback resistor, R FEEDBACK . 4. Guaranteed by design or characterization and not production tested. 5. Accuracy not guaranteed unless outputs at ground potential. 6. Accuracy is tested and guaranteed at V+ = +15V, only.
Definition of Terms
Nonlinearity: Error contributed by deviation of the DAC transfer function from a "best straight line" through the actual plot of transfer function. Normally expressed as a percentage of full scale range or in (sub)multiples of 1 LSB. Resolution: It is addressing the smallest distinct analog output change that a D/A converter can produce. It is commonly expressed as the number of converter bits. A converter with resolution of n bits can resolve output changes of 2-N of the full-scale range, e.g., 2-N VREF for a unipolar conversion. Resolution by no means implies linearity. Settling Time: Time required for the output of a DAC to settle to within specified error band around its final value (e.g., 1/2 LSB) for a given digital input change, i.e., all digital inputs LOW to HIGH and HIGH to LOW. Gain Error: The difference between actual and ideal analog output values at full-scale range, i.e., all digital inputs at HIGH state. It is expressed as a percentage of full scale range or in (sub)multiples of 1 LSB.
Feedthrough Error: Error caused by capacitive coupling from VREF to IOU T1 with all digital inputs LOW. Output Capacitance: Capacitance from IOU T1 , and IOU T2 terminals to ground. Output Leakage Current: Current which appears on IOU T1 , terminal when all digital inputs are LOW or on IOUT2 terminal when all digital inputs are HIGH. For further information on the use of this device, see the following Application Notes:
Application Notes
NOT E # AN002 AN018 AN042 DESCRIPTION " Pr inciples of Data Acquisition and Conversion" " Do's and Don'ts of Applying A/D Converters" " Interpretation of Data Conversion Accuracy Specifications"
3
AD7523, AD7533 Detailed Description
The AD7523 and AD7533 are monolithic multiplying D/A converters. A highly stable thin film R-2R resistor ladder network and NMOS SPDT switches form the basis of the converter circuit, CMOS level shifters permit low power TTL/CMOS compatible operation. An external voltage or current reference and an operational amplifier are all that is required for most voltage output applications. A simplified equivalent circuit of the DAC is shown in the Functional Diagram. The NMOS SPDT switches steer the ladder leg currents between IOUT1 and IOU T2 buses which must be held at ground potential. This configuration maintains a constant current in each ladder leg independent of the input code. Converter errors are further reduced by using separate metal interconnections between the major bits and the outputs. Use of high threshold switches reduce offset (leakage) errors to a negligible level. The level shifter circuits are comprised of three inverters with positive feedback from the output of the second to the first, see Figure 1. This configuration results in TTL/CMOS compatible operation over the full military temperature range. With the ladder SPDT switches driven by the level shifter, each switch is binarily weighted for an ON resistance proportional to the respective ladder leg current. This assures a constant voltage drop across each switch, creating equipotential terminations for the 2R ladder resistors and high accurate leg currents.
±10V +15V V RE F R1 MSB DAT A INPUTS LSB 14 RFEEDBACK 16 AD7523/ 1 OUT1 AD7533 CR1 OUT2 11 3 2 15 4 G ND R2
6 +
VOUT
NOTES: 7. R1 and R2 used only if gain adjustment is required. 8. CR1 protects AD7523 and AD7533 against negative transients. FIGU RE 2. UNIPOLAR BINARY OPERATION
TABLE 1. UNlPOLAR BINARY CODE - AD7523 DIGITAL INPUT MSB LSB 11111111 10000001 10000000 V 01111111 00000001 00000000 ANALOG OUTPUT (VOUT)
V
255 --------R E F 256
129 V R E F --------256
VRE F 128 --------- = ---------------R E F 256 2
127 V R E F --------256 1 V R E F --------256
V+
13 4 6 TO LADDER 8 9
0 VR E F --------- = 0 256
NOTES: 9. 1 LSB = ( 2
Zero Offset Adjustment
1. Connect all digital inputs to GND. 2. Adjust the offset zero adjust trimpot of the output operational amplifier for 0V ±1mV (Max) at V O UT .
TTL/ CMOS INPUT
2
5
7 IOUT2 IOUT1
Gain Adjustment
FIGURE 1. CMOS SWITCH
1. Connect all digital inputs to V+. 2. M onitor VOUT for a -VREF (11/28) reading. 3. To increase VO UT , connect a series resistor, R2, (0 to 250) in the IO UT1 amplifier feedback loop. 4. To decrease VOU T , connect a series resistor, R1, (0 to 250) between the reference voltage and the V R EF terminal.
Typical Applications
Unipolar Binary Operation - AD7523 (8-Bit DAC)
The circuit configuration for operating the AD7523 in unipolar mode is shown in Figure 2. With positive and negative VREF values the circuit is capable of 2-Quadrant multiplication. The "Digital Input Code/Analog Output Value" table for unipolar mode is given in Table 1.
Unipolar Binary Operation - AD7533 (10-Bit DAC)
The circuit configuration for operating the AD7533 in unipolar mode is shown in Figure 2. With positive and negative VREF values the circuit is capable of 2-Quadrant multiplication. The "Digital Input Code/Analog Output Value" table for unipolar mode is given in Table 2.
4
8
1 ) ( VR E F ) = --------- ( VR E F ) . 256
AD7523, AD7533
TABLE 2. UNlP OLAR BINARY CODE - AD7533 DIGITAL INPUT MSB LS B 1111111111 1000000001 1000000000 V 0111111111 0000000001 0000000000 NOTES : 10. V OUT as shown in Figure 2. 11. Nominal Full Scale for the circuit of Figure 2 is given by:
TABLE 3. BlPOLA R (OFFSET BINARY) CODE - AD7523 DIGITAL INPUT MSB LSB 11111111 10000001 10000000 01111111 00000001 00000000 ANALOG OUTPUT
(NOTE 10) NOMINAL ANALOG OUTPUT
0 V R E F ------------ = 0 1024
NOTES: 13. 1 LSB = ( 2
REF
Offset Adjustment
1. Adjust VREF to approximately +10V. 2. Connect all digital inputs to "Logic 1". 3. Adjust IOU T2 amplifier offset adjust trimpot for 0V ±1mV at IOU T2 amplifier output. 4. C onne ct MSB (Bit 1) to "Logic 1" and all other bits to "Logic 0". 5. A djust IO UT1 amplifier offset adjust trimpot for 0V ±1mV at VOU T .
F S = V
1023 ------------ . R E F 1024 1 ------------ . R E F 1024
12. Nominal LSB magnitude for the circuit of Figure 2 is given by: LSB = V
Zero Offset Adjustment
5. Connect all digital inputs to GND. 6. Adjust the offset zero adjust trimpot of the output operational amplifier for 0V ±1mV (Max) at V O UT .
Gain Adjustment
1. Connect all digital inputs to V+. 2. M onitor VOUT for a -VREF (11/28) volts reading. 3. To increase VOU T , connect a series resistor, R2, of up to 250 between V O UT and RFEED BACK . 4. To decrease VOUT , connect a series resistor, R1, of up to 250 between the reference voltage and the VREF terminal.
Gain Adjustment
1. Connect all digital inputs to V+. 2. M onitor VOUT for a -VREF (1 - 1/210) reading. 3. To increase VO UT , connect a series resistor, R2, (0 to 250) in the IO UT1 amplifier feedback loop. 4. To decrease VOU T , connect a series resistor, R1, (0 to 250) between the reference voltage and the V R EF terminal.
Bipolar (Offset Binary) Operation - AD7523
The circuit configuration for operating the AD7523 in the bipolar mode is given in Figure 3. Using offset binary digital input codes and positive and negative reference voltage values, Four-Quadrant multiplication can be realized. The "Digital Input Code/Analog Output Value" table for bipolar mode is given in Table 3.) A "Logic 1" input at any digital input forces the corresponding ladder switch to steer the bit current to IO UT1 bus. A "Logic 0" input forces the bit current to IO UT2 bus. For any code the IOU T1 and IOUT2 bus currents are complements of one another. The current amplifier at IO UT2 changes the polarity of IOU T2 current and the transconductance amplifier at IOUT output sums the two currents. This configuration doubles the output range. The difference current resulting at zero offset binary code, (MSB = "Logic 1", all other bits = "Logic 0"), is corrected by using an external resistor, (10M), from VREF to IOUT2 (Figure 3). 5
Bipolar (Offset Binary) Operation - AD7533
The circuit configuration for operating the AD7533 in the bipolar mode is given in Figure 3. Using offset binary digital input codes and positive and negative reference voltage values, 4-Quadrant multiplication can be realized. The "Digital Input Code/Analog Output Value" table for bipolar mode is given in Table 4. A "Logic 1" input at any digital input forces the corresponding ladder switch to steer the bit current to IOU T1 bus. A "Logic 0" input forces the bit current to IO UT2 bus. For any code the IO U T1 and IOU T2 bus currents are complements of one another. The current amplifier at IOU T2 changes the polarity of IOU T2 current and the transconductance amplifier at IO U T1 output sums the two currents. This configuration doubles the output range. The difference current resulting at zero offset binary code, (MSB = "Logic 1", all other bits = "Logic 0"), is corrected by using an external resistor, (10M), from VR EF to IO UT2 .
7
)( V
)=
1 --------- ( V ). RE F 128
1 V R E F -----------1024
+V
128 --------R E F 128
511 V R E F -----------1024
127 +VR E F --------128
512 -----------R E F 1024
VR E F = -------------2
0 +V 1 --------R E F 128
513 V R E F -----------1024
V
1 --------R E F 128
1023 V R E F -----------1024
127 V R E F --------128
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