Programmable Schmitt Trigger with Memory, Dual Input Precision Level Detector
The CA3098 Programmable Schmitt Trigger is a monolithic silicon integrated circuit designed to control high operating current loads such as thyristors, lamps, relays, etc. The CA3098 can be operated with either a single power supply with maximum operating voltage or a dual power supply with maximum operating voltage ±8V. It can directly control currents to 150mA and operates with microwatt standby power dissipation when the current to be controlled is less than 30mA. The CA3098 contains the following major circuit function features (see Block Diagram): 1. Differential amplifiers and summer: the circuit uses two differential amplifiers, one to compare the input voltage with the "high" reference, and the other to compare the input with the "low" reference. The resultant output of the differential amplifiers actuates a summer circuit which delivers a trigger that initiates a change in state of a flipflop. 2. Flip-flop: the flip-flop functions as a bistable "memory" element that changes state in response to each trigger command. 3. Driver and output stages: these stages permit the circuit to "sink" maximum peak load currents 150mA at terminal 3. 4. Programmable operating current: the circuit incorporates access at terminal 2 to permit programming the desired quiescent operating current and performance parameters.
· Programmable Operating Current· Micropower Standby Dissipation· Direct Control of Currents Up to. 150mA· Low Input On/Off Current of Less Than 1nA for Programmable Bias Current of 1µA· Built-in Hysteresis. 20mV (Max)
· Control of Relays, Heaters, LEDs, Lamps, Photosensitive Devices, Thyristors, Solenoids, etc.· Signal Reconditioning· Phase and Frequency Modulators· On/Off Motor Switching· Schmitt Triggers, Level Detectors· Time Delays· Overvoltage, Overcurrent, Overtemperature Protection· Battery-Operated Equipment· Square and Triangular-Wave Generators
PART NUMBER CA3098E TEMP RANGE ( oC) to 125 PACKAGE 8 Ld PDIP PKG. NO. E8.3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2001. All Rights Reserved
2 PROGRAMMABLE BIAS CURRENT INPUT (IBIAS) 6 V+ OUTPUT CURRENT CONTROL 5 DIFF. AMP "SINK OUTPUT" SUMMER FLIP-FLOP (MEMORY) DRIVER OUTPUT 3
Q20 Q24 OUTPUT CURRENT CONTROL Q41 Q26 SIGNAL INPUT R14 500 "SINK" OUTPUT Q39 V+
Supply Voltage Between V+ and V-.16V Voltage Between High Reference or Sink Output and V-.16V Differential Input Voltage Between Terminals 8 and 1.10V and Terminals 7 and 8 Load Current (Terminal 3) (Duty Cycle 25%). 150mA Input Current to Voltage Regulator (Terminal 5). 25mA Programmable Bias Current (Terminal 2). 1mA Output Current Control (Terminal 5). 15mA
Thermal Resistance (Typical, Note 3) JA PDIP Package. 125oC/W Maximum Junction Temperature (Die). 175oC Maximum Junction Temperature (Plastic Package). 150oC Maximum Storage Temperature Range. to 150oC Maximum Lead Temperature (Soldering 10s). 300oC
Temperature Range. to 125oC Voltage Range +IN. to V+ HIGH REF. (V- to V+ LOW REF. (V-) to (V+ -2.0V)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
= 25oC, Unless Otherwise Specified CA3098 SYMBOL VIO(LR) VIO(HR) TEST CONDITIONS VLR = GND, V+ to (V- +2V), IBIAS = 100µA VHR = GND, V- to (V+ -2V), IBIAS to 125oC VIO(HRLR)
PARAMETER Input Offset Voltage "Low" Reference (Figures 2, 5) "High Reference (Figures 2, 6) Temperature Coefficient "Low" Reference (Figure 7) "High" Reference (Figure 8) Minimum Hysteresis Voltage (Figure 9) Temperature Coefficient (Figure 10) Output Saturation Voltage (Figures 11, 12) Total Supply Current "ON" (Figures 13, 14) "OFF" (Figures 13, 14) Input Bias Current (Figures 3, 15) IB(PNP) IB(NPN) Output Leakage Current Switching Times (Figures 4, 16-27) Delay Time Fall Time Rise Time Storage Time Output Current (Note 2)
VCE(SAT) = 5V, VREG = 6V (Note = 12V, IBIAS = 100µA ITOTAL = 6V, VREG > 6V (Note = 16V, IBIAS = 10V, VREG < 10V (Note = 16V, IBIAS = 100µA IIB = 16V, VREG < 16V (Note = 16V, IBIAS = 6V, VREG > 6V (Note = 16V, IBIAS = 100µA ICE(OFF) tS IO Current from Terminal 3 when Q46 is "OFF" IBIAS 5V, V REG = 2.5V (Note 1)
NOTES: 1. For definition of VREG see Figure 3. 2. Continuous (DC) output current must be limited to 40mA. For 100mA output current, the duty cycle must JA is measured with the component mounted on an evaluation PC board in free air.