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Part: CA3282AS2
Category:
Logic
-> Bus Exchangers
Description: Octal Low Side Power Driver With Serial Bus Control
Company: Intersil Corporation
Datasheet: Download CA3282AS2 datasheet File size : 1382 kB
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CA3282
June 1998
Octal Low Side Power Driver with Serial Bus Control
Description
The CA3282 is a logic controlled, eight channel octal power driven. The serial peripheral interface (SPI) utilized by the CA3282 is a serial synchronous bus compatible with Intersil CDP68HC05, or equivalent, microcomputers. As shown in the Block Diagram for the CA3282 each of the open drain NDMOS output drivers has individual protection for over-voltage and over-current. Each output channel has separate output latch control with fault unlatch and diagnostic feedback. Under normal ON conditions, each output driver is in a low, saturation state. Comparators in the diagnostic circuitr y monitor the output drivers to determine if an out of saturation condition exists. If a comparator senses a fault, the respective output driver is unlatched. In addition, over current protection is provided with current limiting in each output, independent of the diagnostic feedback loop. The CA3282 is fabricated in a Power BiMOS IC process, and is intended for use in automotive and other applications having a wide range of temperature and electrical stress conditions. It is particularly suited for driving lamps, relays, and solenoids in applications where low operating power, high breakdown voltage, and high output current at high temperatures is required. The CA3282 is supplied in 15 lead plastic SIP package with lead forms for either vertical or surface mount.
Features
· Output Current Drive Capability - All Outputs ON, Equal . . . . . . . . . . . . . . 0.625A Each - Per Output Individually . . . . . . . . . . . . . . . . . 1A Each - Maximum Total of Outputs ON . . . . . . . . . . . . . . . .5A · High Voltage Power BiMOS Outputs - 8 Open Drain NDMOS Drivers - Individual Output Latch - Over-Current Limit Protection . . . . . . . . . . . . . 1.05A - Over-Voltage Clamp Protection. . . . . . . . . . . . . . . 30V · High Speed CMOS Logic Control - Low Quiescent IDD Current . . . . . . . . . . . . . . . . . 5mA - SPI Bus Controlled Interface - Individual Fault Unlatch and Feedback - Common Reset Line · Operating Temperature Range . . . . . . . -40oC to 125oC
Applications
· Automotive and Industrial Systems · Solenoids, Relays and Lamp Drivers · Logic and µP Controlled Drivers · Robotic Controls
Ordering Information
PART NUMBER CA3282AS1 CA3282AS2 TEMP. RANGE(oC) -40 to 125 -40 to 125 PACKAGE AND LEAD FORM 15 Ld Plastic SIP Staggered Vertical 15 Ld Plastic SIP Surface Mount PKG NO. Z15.05A Z15.05B
Pinout
CA3282 (SIP) TOP VIEW
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 OUTPUT 4 OUTPUT 5 OUTPUT 6 OUTPUT 7 RESET VDD
MISO VSS MOSI SCK CE
Block Diagram
OUTPUT #0 (1 OF 8)
NOTE: HEAT SINK TAB INTERNALLY CONNECTED TO GROUND (VSS)
MOSI SCK MISO CE RESET
SPI INTERFACE CIRCUIT
SHIFT REGISTER
OUTPUT LATCH CURRENT LIMIT
OUTPUT 0 OUTPUT 1 OUTPUT 2 OUTPUT 3
CONTROL LOGIC
DIAGNOSTIC CIRCUITRY
TO DRIVERS 1 THRU 7
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
File Number
2767.6
1
CA3282
Absolute Maximum Ratings
Output Voltage, VO (Note 1) . . . . . . . . . . . . . . . . . . . . . VOC (Clamp) Output Load Current, ILOAD (Per Output, Individual) . . . . . . . . . 1A Output Load Current, ILOAD (All 8 Outputs ON, Equal IOUT) . . . . . 0.625A Output Load Current, ILOAD (Max. Total of Outputs ON) . . . . 5.0A DC Logic Supply, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.7 to +7V
Thermal Information
Thermal Resistance (Typical, Note 2) JA(oC/W) JC(oC/W) Plastic SIP No Heat Sink . . . . . . . . . . . . . . . . . . . 45 N/A Infinite Heat Sink . . . . . . . . . . . . . . . . . N/A 3 Power Dissipation Up to 125oC w/o Heat Sink . . . . . . . . . . . . . . . . . . . . . . . . 0.56W Above 125oC w/o Heat Sink . . . . . . .Derate Linearly at 22mW/oC Up to 125oC w/Infinite Heat Sink. . . . . . . . . . . . . . . . . . . . 8.33W Above 125oC w/Infinite Heat Sink. . . . Derate Linearly at 333mW/oC Maximum Storage Temperature Range . . . . . . . . . -55oC to 150oC Maximum Lead Temperature (Soldering, 10s). . . . . . . . . . . . . . . 265oC
Operating Conditions
Ambient Temperature Range . . . . . . . . . . . . . . . . . -40oC to 125oC Junction Temperature Range . . . . . . . . . . . . . . . . . -40oC to 150oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. The MOSFET Output Drain is internally clamped with a Drain-to-Gate zener diode that turns-on the MOSFET; holding the Drain at the Output Clamp Voltage, VOC. 2. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER Quiescent Supply Current, ON Quiescent Supply Current, OFF Output Clamping Voltage Output Clamping Energy Output Leakage Current
VDD = 5V, TA = -40oC to 125oC, Unless Otherwise Specified SYMBOL IDD IDD VOC EOC IO LEAK TEST CONDITIONS All Outputs ON, 0.5A Load Per Output All Outputs OFF ILOAD = 0.5A, Output Programmed OFF ILOAD = 0.5A, Output ON Output Programmed OFF VO = 24V VO = 14V VO = 5V MIN 27 20 1.05 1.6 50 TYP 5 0.2 32 150 150 150 1.5 1 2 1.8 80 0 MAX 10 40 1000 500 200 1 10 10 2.0 250 1 UNITS mA mA V mJ µA µA µA A µs µs V µs V
Output ON Resistance Output Current Limit Turn-On Delay Turn-Off Delay Fault Reference Voltage Fault Reset Delay (After CE Low to High Transition) Output OFF Voltage LOGIC INPUTS
rDS(ON) IO LIMIT tPHL tPLH VOREF tUD VOFF
ILOAD = 0.5A (Note 3) Output Programmed ON, VOUT > 3V IO = 500mA, No Reactive Load IO = 500mA, No Reactive Load Output Programmed ON, Fault Detected If VO > VOREF See Figure 1 Output Programmed OFF, Output Pin Floating
(MOSI, CE, SCK and RESET) VTVT+ VH II CI (MISO) VOL VOH IOL = 1.6mA IOL = 0.8mA VDD - 1.3V 0.2 VDD - 0.2V 0.4 V V VDD = 5V ± 10% VDD = 5V ± 10% VT+ - VTVDD = 5.5V, 0 < VI < VDD 0 < VI < VDD 0.2VDD 0.85 -10 0.3VDD 0.6VDD 1.4 0.7VDD 2.25 +10 20 V V V µA pF
Threshold Voltage at Falling Edge Threshold Voltage at Rising Edge Hysteresis Voltage Input Current Input Capacitance LOGIC OUTPUT
Output LOW Voltage Output HIGH Voltage
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CA3282
Electrical Specifications
PARAMETER Output Three State Leakage Current Output Capacitance VDD = 5V, TA = -40oC to 125oC, Unless Otherwise Specified (Continued) SYMBOL IOL COUT TEST CONDITIONS VDD = 5.25V, 0 < VO < VDD , CE Pin Held High 0 < VO < VDD, CE Pin Held High MIN -10 TYP MAX +10 20 UNITS µA pF
Serial Peripheral Interface Timing (See Figure 1B)
PARAMETER Operating Frequency Enable Lead Time Enable Lag Time Clock HIGH Time Clock LOW Time Data Setup Time Data Hold Time Enable Time Disable Time Data Valid Time Output Data Hold Time Rise Time (MISO Output) Rise Time SPI Inputs (SCK, MOSI, CE) Fall Time (MISO Output) Fall Time SPI Inputs (SCK, MOSI, CE) NOTES: 3. Refer to Figure 4A for IOUT current vs VSAT voltage. Typical rDS(ON) values are given for -40oC, 25oC, 105oC and 125oC temperatures. 4. The Maximum Operating Frequency is typically greater than 10MHz but it is application limited primarily by external SPI input rise/fall times and MISO output loading. SYMBOL fOPER (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (12) (13) (13) tLEAD tLAG twSCK
H
TEST CONDITIONS
MIN D.C. 0
TYP Note 4 <100 <100 50 50 20 20 50 150 75 50 35 45 -
MAX 3.0 200 200 100 100 50 50 100 300 150 100 50 100 50
UNITS MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns
twSCK
L
tSU tH tEN tDIS tV tHO trSO trSI tfSO tfSI VDD = 20% to 70%, CL = 200pF VDD = 20% to 70%, CL = 200pF VDD = 70% to 20%, CL = 200pF VDD = 70% to 20%, CL = 200pF
-
Timing Diagrams
CE
SCK (CPOL = 0, CPHA = 1)
MSB
6
5
4
3
2
1
LSB
INTERNAL STROBE FOR DATA CAPTURE
FIGURE 1A. DATA AND CLOCK TIMING DIAGRAM
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CA3282 Timing Diagrams
CE (INPUT) (2) SCK (INPUT) LAST BIT TRANSMITTED (5) (4) (1) (13) (12) (3)
(Continued)
MISO (OUTPUT)
HIGH Z
D70 (8) (10) D71 (6) (7)
D60 (11) D61
D10 (9) D11 FAULT-INDUCED TURN-OFF
MOSI (INPUT)
DRIVER OUTPUT
OLD tPHL tPLH
NEW
tUD
FIGURE 1B.
SPI TIMING DIAGRAM
RESET
CE
SCK
MOSI
7
6
5
4
3
2
1
0
MISO
7
6
5
4
3
2
1
0
OUTPUTS
OLD
NEW FAULTS
RESET
FIGURE 2. BYTE TIMING DIAGRAM WITH ASYNCHRONOUS RESET
Signal Descriptions
Power Output Drivers, Output 0 - Output 7 - The input and output bits corresponding to Output 0 thru Output 7 are transmitted and received most significant bit (MSB) first via the SPI bus. The outputs are provided with current limiting and voltage sense functions for fault indication and protection. The nominal load current for these outputs is 500mA, with current limiting set to a minimum of 1.05A. An on-chip clamp circuit capable of handling 500mA is provided at each output for clamping inductive loads. RESET - Active low reset input. When this input line is low, the shift register and output latches are configured to turn off
all output drivers. A power on clear function may be implemented by connecting this pin to VDD with an external resistor, and to VSS with an external capacitor. In any case, this pin must not be left floating. CE - Active low chip enable. Data is transferred from the shift register to the outputs on the rising edge of this signal. The falling edge of CE loads the shift register with the output voltage sense bits coming from the output stages. The output driver for the MISO pin is enabled when this pin is low. CE must be a logic low prior to the first serial clock (SCK) and must remain low until after the last (eighth) serial clock cycle. A low level on CE also activates an internal disable circuit used for unlatching output states that are in a fault mode as
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CA3282
sensed by an out of saturation condition. A high on CE forces MISO to a high impedance state. Also, when CE is high, the octal driver ignores the SCK and MOSI signals. SCK, MISO, MOSI - See Serial Peripheral Interface (SPI) section in this data sheet. VDD and VSS (GND) - Positive and negative power supply lines. Serial Peripheral Interface (SPI) The Serial Peripheral Interface (SPI) utilized by the CA3282 is a serial synchronous bus for control and data transfers. The Clock (SCK), which is generated by the microcomputer, is active only during data transfers. In systems using CDP68HC05 family microcomputers, the inactive clock polarity is determined by the CPOL bit in the microcomputer's control register. The CPOL bit is used in conjunction with the clock phase bit, CPHA to produce the desired clock data relationship between the microcomputer and octal driver. The CPHA bit in general selects the clock edge which captures data and allows it to change states. For the CA3282, the CPOL bit must be set to a logic zero and the CPHA bit to a logic one. Configured in this manner, MISO (output) data will appear with ever y rising edge SCK, and MOSI (input) data will be latched into the shift register with every falling edge of SCK. Also, the steady state value of the inactive serial clock, SCK, will be at a low level. Timing diagrams for the serial peripheral interface are shown in Figure 1. SPI Signal Descriptions MOSI (Master Out/Slave In) - Serial data input. Data bytes are shifted in at this pin, most significant bit (MSB) first. The data is passed directly to the shift register which in turn controls the latches and output drivers. A logic "0" on this pin will program the corresponding output to be ON, and a logic "1" will turn it OFF. MISO (Master In/Slave Out) - Serial data output. Data bytes are shifted out at this pin, most significant bit (MSB) first. This pin is the serial output from the shift register and is three stated when CE is high. A high for a data bit on this pin indicates that the corresponding output is high. A low on this pin for a data bit indicates that the output is low. Comparing the serial output bits with the previous input bits, the microcomputer implements the diagnostic data supplied by the CA3282. SCK - Serial clock input. This signal clocks the shift register SCK and new MOSI (input) data will be latched into the shift register on every falling edge of SCK. The SCK phase bit, CPHA, and polarity bit, CPOL, must be set to 1 and 0, respectively in the microcomputer's control register. Serial Peripheral Interface (SPI) protocol. Each channel is independently controlled by an output latch and a common RESET line that disables all eight outputs. Byte timing with asynchronous reset is shown in Figure 4. The circuit receives 8-bit serial data by means of the serial input (MOSI), and stores this data in an internal register to control the output drivers. The serial output (MISO) provides 8-bit diagnostic data representing the voltage level at the driver output. This allows the microcomputer to diagnose the condition at the output drivers. The device is selected when the chip enable (CE) line is low. When (CE) is high, the device is deselected and the serial output (MISO) is placed in a threestate mode. The device shifts serial data on the rising edge of the serial clock (SCK), and latches data on the falling edge. On the rising edge of chip enable (CE), new input data from the shift register is latched in the output drivers. The falling edge of chip enable (CE) transfers the output drivers fault information back to the shift register. The output drivers have low ON voltage at rated current, and are monitored by a comparator for an out of saturation condition, in which case the output driver with the fault becomes unlatched and diagnostic data is sent to the microcomputer via the MISO line. A typical microcomputer interface circuit is shown in Figure 2. Also, the CA3282 may be cascaded with another CA3282 octal driver. Shift Register The shift register has both serial and parallel inputs and outputs. Serial output and input data are simultaneously transferred to and from the SPI bus. The parallel outputs are latched into the output latch in the CA3282 at the end of a data transfer. The parallel inputs jam diagnostic data into the shift register at the beginning of a data transfer cycle.
CDP68HC05C4 MICROCOMPUTER PORT MOSI MISO SCK RESET CE MOSI MISO SCK
CA3282
RESET
FIGURE 3. TYPICAL MICROCOMPUTER INTERFACE WITH THE CA3282
Output Latch The output latch holds input data from the shift register which is used to activate the outputs. The latch circuit may be cleared by a fault condition (to protect the overloaded outputs), or by the RESET signal.
Functional Descriptions
The CA3282 is a low operating power, high voltage, high current, octal power driver featuring eight channels of open drain NDMOS output drivers. The drivers have low saturation voltage and output shor t circuit protection, suited for driving resistive or inductive loads such as lamps, relays and solenoids. Data is transmitted to the device serially using the
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