|
|
Part: CD4030BMS
Category:
Logic
-> Gates
-> CMOS/BiCMOS->4000 Family
Description: Radiation Hardened CMOS Quad Exclusive-OR GATE
Company: Intersil Corporation
Datasheet: Download CD4030BMS datasheet File size : 495 kB
Request For quote: Find where to buy CD4030BMS
Datasheet text preview:
CD4030BMS
December 1992
CMOS Quad Exclusive-OR Gate
Pinout
CD4030BMS TOP VIEW
Features
· High Voltage Type (20V Rating) · Medium-Speed Operation - tPHL, tPLH = 65ns (typ) at VDD = 10V, CL = 50pF · 100% Tested for Quiescent Current at 20V · Standardized Symmetrical Output Characteristics · 5V, 10V and 15V Parametric Ratings · Maximum Input Current Of 1µA at 18V Over Full Package-Temperature Range; - 100nA at 18V and +25oC · Noise Margin (Over Full Package Temperature Range): - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V · Meets All Requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of `B' Series CMOS Devices"
A1 B2 J=AB 3 K=CD 4 C5 D6 VSS 7
14 VDD 13 H 12 G 11 M = G H 10 L = E F 9F 8E
Functional Diagram
A B 1 2 3
Applications
· Even and Odd-Parity Generators and Checkers · Logical Comparators · Adders/Subtractors · General Logic Functions
J
C D
5 6
4
K
Description
The CD4030BMS types consist of four independent Exclusive-OR gates. The CD4030BMS provides the system designer with a means for direct implementation of the Exclusive-OR function. The CD4030BMS is supplied in these 14-lead outline packages: Braze Seal DIP H4H Frit Seal DIP H1B Ceramic Flatpack H3W
E F
8 9
10
L
12 G H 13
11
M
J=AB K=CD VSS = 7 VDD = 14
M=GH L=EF
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
File Number
3305
7-317
Specifications CD4030BMS
Absolute Maximum Ratings
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum
Reliability Information
Thermal Resistance . . . . . . . . . . . . . . . . ja jc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC//W o Maximum Package Power Dissipation (PD) at +125 C For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS 1 2 VDD = 18V, VIN = VDD or GND Input Leakage Current IIL VIN = VDD or GND VDD = 20 3 1 2 VDD = 18V Input Leakage Current IIH VIN = VDD or GND VDD = 20 3 1 2 VDD = 18V Output Voltage Output Voltage Output Current (Sink) Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) Output Current (Source) Output Current (Source) N Threshold Voltage P Threshold Voltage Functional VOL15 VOH15 IOL5 IOL10 IOL15 IOH5A IOH5B IOH10 IOH15 VNTH VPTH F VDD = 15V, No Load VDD = 15V, No Load (Note 3) VDD = 5V, VOUT = 0.4V VDD = 10V, VOUT = 0.5V VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V VDD = 5V, VOUT = 2.5V VDD = 10V, VOUT = 9.5V VDD = 15V, VOUT = 13.5V VDD = 10V, ISS = -10µA VSS = 0V, IDD = 10µA VDD = 2.8V, VIN = VDD or GND VDD = 20V, VIN = VDD or GND VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Input Voltage Low (Note 2) Input Voltage High (Note 2) Input Voltage Low (Note 2) Input Voltage High (Note 2) VIL VIH VIL VIH VDD = 5V, VOH > 4.5V, VOL 4.5V, VOL 13.5V, VOL 13.5V, VOL < 1.5V 3 1, 2, 3 1, 2, 3 1 1 1 1 1 1 1 1 1 7 7 8A 8B 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 LIMITS TEMPERATURE +25
oC
PARAMETER Supply Current
SYMBOL IDD
CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND
MIN -100 -1000 -100 -
MAX 2 200 2 100 1000 100 50 -0.53 -1.8 -1.4 -3.5 -0.7 2.8
UNITS µA µA µA nA nA nA nA nA nA mV V mA mA mA mA mA mA mA V V V
+125oC -55oC +25o C
+125oC -55oC +25oC +125oC -55oC +25oC, +125oC, -55oC
+25oC, +125oC, -55oC 14.95 +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25 C +25 C +25oC +125oC -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC 3.5 11
o o
0.53 1.4 3.5 -2.8 0.7
VOH > VOL < VDD/2 VDD/2
1.5 4 -
V V V V
NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs.
3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max.
7-318
Specifications CD4030BMS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS TEMPERATURE 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 +25oC +125oC, -55oC LIMITS MIN MAX 280 378 200 270 UNITS ns ns ns ns
PARAMETER Propagation Delay
SYMBOL TPHL TPLH TTHL TTLH
CONDITIONS (NOTE 1, 2) VDD = 5V, VIN = VDD or GND
Transition Time
+25oC +125oC, -55oC
NOTES: 1. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD CONDITIONS VDD = 5V, VIN = VDD or GND NOTES 1, 2 TEMPERATURE -55 C, +25 C +125 C VDD = 10V, VIN = VDD or GND 1, 2 -55oC, +25oC +125oC VDD = 15V, VIN = VDD or GND 1, 2 -55oC, +25oC +125oC Output Voltage Output Voltage Output Voltage Output Voltage Output Current (Sink) VOL VOL VOH VOH IOL5 VDD = 5V, No Load VDD = 10V, No Load VDD = 5V, No Load VDD = 10V, No Load VDD = 5V, VOUT = 0.4V 1, 2 1, 2 1, 2 1, 2 1, 2 +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +125oC -55oC Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1, 2 +125 C -55oC Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1, 2 +125oC -55 Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1, 2
oC o o o o
MIN 4.95 9.95 0.36 0.64 0.9 1.6 2.4 4.2 -
MAX 1 30 2 60 2 120 50 50 -0.36 -0.64 -1.15 -2.0 -0.9 -1.6 -2.4 -4.2 3 130 100
UNITS µA µA µA µA µA µA mV mV V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA V V ns ns
+125oC -55oC +125oC -55oC
o
Output Current (Source)
IOH5B
VDD = 5V, VOUT = 2.5V
1, 2
Output Current (Source)
IOH10
VDD = 10V, VOUT = 9.5V
1, 2
+125 C -55 C
o
Output Current (Source)
IOH15
VDD =15V, VOUT = 13.5V
1, 2
+125oC -55oC
o o
Input Voltage Low Input Voltage High Propagation Delay
VIL VIH TPHL TPLH
VDD = 10V, VOH > 9V, VOL 9V, VOL < 1V VDD = 10V VDD = 15V
1, 2 1, 2 1, 2, 3 1, 2, 3
+25 C, +125 C, -55oC +25oC, +125oC, -55oC +25oC +25oC
7 -
7-319
Specifications CD4030BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Transition Time SYMBOL TTHL TTLH CIN CONDITIONS VDD = 10V VDD = 15V Any Input NOTES 1, 2, 3 1, 2, 3 1, 2 TEMPERATURE +25oC +25 C +25oC
o
MIN -
MAX 100 80 7.5
UNITS ns ns pF
Input Capacitance NOTES:
1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current N Threshold Voltage N Threshold Voltage Delta P Threshold Voltage P Threshold Voltage Delta Functional SYMBOL IDD VNTH VTN VTP VTP F CONDITIONS VDD = 20V, VIN = VDD or GND VDD = 10V, ISS = -10µA VDD = 10V, ISS = -10µA VSS = 0V, IDD = 10µA VSS = 0V, IDD = 10µA VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Propagation Delay Time TPHL TPLH VDD = 5V 1, 2, 3, 4 +25oC NOTES 1, 4 1, 4 1, 4 1, 4 1, 4 1 TEMPERATURE +25 C +25oC +25oC +25oC +25oC +25oC
o
MIN -2.8 0.2 VOH > VDD/2 -
MAX 7.5 -0.2 ±1 2.8 ±1 VOL < VDD/2 1.35 x +25oC Limit
UNITS µA V V V V V
ns
NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
3. See Table 2 for +25oC limit. 4. Read and Record
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC PARAMETER Supply Current - MSI-1 Output Current (Sink) Output Current (Source) SYMBOL IDD IOL5 IOH5A ± 0.2µA ± 20% x Pre-Test Reading ± 20% x Pre-Test Reading DELTA LIMIT
TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUP Initial Test (Pre Burn-In) Interim Test 1 (Post Burn-In) Interim Test 2 (Post Burn-In) PDA (Note 1) Interim Test 3 (Post Burn-In) PDA (Note 1) Final Test Group A MIL-STD-883 METHOD 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 Sample 5005 GROUP A SUBGROUPS 1, 7, 9 1, 7, 9 1, 7, 9 1, 7, 9, Deltas 1, 7, 9 1, 7, 9, Deltas 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 IDD, IOL5, IOH5A READ AND RECORD IDD, IOL5, IOH5A IDD, IOL5, IOH5A IDD, IOL5, IOH5A
7-320
Specifications CD4030BMS
TABLE 6. APPLICABLE SUBGROUPS (Continued) CONFORMANCE GROUP Group B Subgroup B-5 Subgroup B-6 Group D MIL-STD-883 METHOD Sample 5005 Sample 5005 Sample 5005 GROUP A SUBGROUPS 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas 1, 7, 9 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3 READ AND RECORD Subgroups 1, 2, 3, 9, 10, 11
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
TABLE 7. TOTAL DOSE IRRADIATION MIL-STD-883 METHOD 5005 TEST PRE-IRRAD 1, 7, 9 POST-IRRAD Table 4 READ AND RECORD PRE-IRRAD 1, 9 POST-IRRAD Table 4
CONFORMANCE GROUPS Group E Subgroup 2
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION Static Burn-In 1 Note 1 Static Burn-In 2 Note 1 Dynamic BurnIn Note 1 Irradiation Note 2 NOTE: 1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V ± 0.5V OPEN 3, 4, 10, 11 3, 4, 10, 11 3, 4, 10, 11 GROUND 1, 2, 5 - 9, 12, 13 7 7 7 VDD 14 1, 2, 5, 6, 8, 9, 12 - 14 14 1, 2, 5, 6, 8, 9, 12 - 14 3, 4, 10, 11 2, 6, 9, 13 1, 5, 8, 12 9V ± -0.5V 50kHz 25kHz
Schematic Diagram
VDD VDD p B* 2(5, 9, 12) n n p VSS VDD n p A* 1(6, 8, 13) n VDD VSS VSS p n p J 3(4, 10, 11) p
TRUTH TABLE FOR 1 OF 4 INDENTICAL GATES A 0 1 0 1 1 = High Level 0 = Low Level B 0 0 1 1 J 0 1 1 0
*INPUTS PROTECTED
BY CMOS PROTECTION NETWORK VSS
FIGURE 1. 1 OF 4 IDENTICAL GATES
7-321
Others parts begin by cd
CD-1 CD-2 CD-3 CD-4 CD-5 CD-6 CD-7 CD-8 CD-9 CD-10 CD-11 CD-12 CD-13 CD-14 CD-15 CD-16 CD-17 CD-18 CD-19 CD-20 CD-21 CD-22 CD-23 CD-24 CD-25 CD-26 CD-27 CD-28 CD-29 CD-30 CD-31 CD-32 CD-33 CD-34 CD-35 CD-36 CD-37
|
|
|
