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Part: CDP1805ACE
Category:
Description: CMOS 8-bit Microprocessor With On-chip RAM And Counter/timer
Company: Intersil Corporation
Datasheet: Download CDP1805ACE datasheet File size : 31 kB
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TM
CDP1805AC, CDP1806AC
CMOS 8-Bit Microprocessor with On-Chip RAM and Counter/Timer
Description
The CDP1805AC and CDP1806AC are functional and performance enhancements of the CDP1802 CMOS 8-bit register-oriented microprocessor series and are designed for use in general-purpose applications. The CDP1805AC hardware enhancements include a 64byte RAM and an 8-bit presettable down counter. The Counter/Timer which generates an internal interrupt request, can be programmed for use in timebase, event-counting, and pulse-duration measurement applications. The Counter/Timer underflow output can also be directed to the Q output terminal. The CDP1806AC hardware enhancements are identical to the CDP1805AC, except the CDP1806AC contains no on-chip RAM. The CDP1805AC and CDP1806AC software enhancements include 32 more instructions than the CDP1802. The 32 new software instructions add subroutine call and return capability, enhanced data transfer manipulation, Counter/Timer control, improved interrupt handling, single-instruction loop counting, and BCD arithmetic. Upwards software and hardware compatibility is maintained when substituting a CDP1805AC or CDP1806AC for other CDP1800-series microprocessors. Pinout is identical except for the replacement of VCC with ME on the CDP1805AC and the replacement of VCC with VDD on the CDP1806AC.
March 1997
Features
· Instruction Time of 3.2µs, -40oC to +85oC · 123 Instructions - Upwards Software Compatible With CDP1802 · BCD Arithmetic Instructions · Low-Power IDLE Mode · Pin Compatible With CDP1802 Except for Terminal 16 · 64K-Byte Memory Address Capability · 64 Bytes of On-Chip RAM · 16 x 16 Matrix of On-Board Registers · On-Chip Crystal or RC Controlled Oscillator · 8-Bit Counter/Timer
n
Ordering Information
CDP 1805AC CDP18 05ACE CDP18 05ACQ CDP18 05ACD CDP18 05ACDX CDP1806AC CDP 1806A CE CDP 1806A CEX CDP 1806A CQ CDP 1806A CD -40oC to +85oC -40oC to +85oC TEMPERATURE RANGE -40oC to +85oC P ACKAGE Plastic DIP B urn-I n PLCC SBD IP B urn-I n N44. 65 D 40. 6 E40.6 PKG. NO.
CDP1805AC Only
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved 1
File Number
1370.2
CDP1805AC, CDP1806AC Pinouts
CDP1805AC, CDP1806AC (PDIP, SBDIP) TOP VIEW
CLOCK WAIT CL EAR Q SC1 SC0 M RD BUS 7 BUS 6 1 2 3 4 5 6 7 8 9 40 VDD 38 DMA IN XTAL WAIT VD D SC1 Q 37 DMA OUT 36 INTERRUPT 35 MWR 34 TPA 33 TPB 32 MA7 31 MA6 30 MA5 29 MA4 28 MA3 27 MA2 26 MA1 25 MA0 24 EF1 23 EF2 22 EF3 21 EF4 SC0 M RD BU S 7 BU S 6 BU S 5 NC BU S 4 BU S 3 BU S 2 BU S 1 BU S 0 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 MA0 EF3 VSS EF4 EF2 EF1 NC N2 N1 N0 CL OCK NC CL EAR INT E RRUPT 39 XTAL DMA - IN DMA - OUT
CDP1805AC, CDP1806AC (PLCC, PACKAGE TYPE Q) TOP VIEW
6 5 4 3 2 1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 M WR TPA TPB M A7 M A6 NC M A5 M A4 M A3 M A2 M A1
BUS 5 10 BUS 4 11 BUS 3 12 BUS 2 13 BUS 1 14 BUS 0 15 16 N2 17 N1 18 N0 19 VSS 20
ME for CDP1805AC VDD for CDP1806AC
Schematic
ADDRESS BUS
MA0 - MA7 MRD IN CDP1851 PIO CONT ROL CDP1805AC WITH RAM, COUNTER/TIMER CDP1806AC WITH COUNTER/TIMER MWR OUT BUS0 - BUS7 BUS0 - BUS7 TPA ME TPA
MA0 - MA7
M RD
MA0-MA4
CDP1833 1K BYTE ROM
CDP1824 32 BYTE RAM (USED WITH CDP1806AC ONLY) MWR
BUS0 - BUS7 (CDP1805AC ONLY)
CEO
CS
BUS0-BUS4
8-BIT DATA BUS
FIGURE 1. TYPICAL CDP1805AC, CDP1806AC SMALL MICROPROCESSOR SYSTEM
2
I/O REQUESTS MEMORY ADDRESS LINES M A7 M A5 M A3 M A1 M A6 M A4 M A2 M A0 CLEAR WAIT EF1 EF3 EF2 EF4 DMA OUT DM A IN INT I/O FLAGS CONT ROL
ME FOR CDP1805AC VDD FOR CDP1806AC M UX 64-BYTE RAM CONTROL AND TIMING LOGIC CL OCK LOGIC
CDP1805AC ONLY
CL OCK
COUNTER HOLDING REGISTER (CH) MODE CONTROL CLK INT E RRUPT LOGIC A (16) AL U DF (1) R(0).1 R(0).0 R(1).1 R(1).0 R(2).1 R(2).0 R(9).1 R(9).0 R(A).1 R(A).0 R(E).1 R(E).0 R(F).1 R(F).0 REGISTER ARRAY R INCR/ DECR EF1 EF2 TPA
8-BIT COUNTER / TIMER
÷ 32
TC INSTRUCTION DECODE
XTAL SCO STATE CO DES SCI Q LOGIC TPA TPB SYSTEM TIMING M WR M RD
CDP1805AC, CDP1806AC
FIGURE 2. BLOCK DIAGRAM FOR CDP1805AC AND CDP1806AC
3
B (8) D (8) LATCH AND DECODE 8-BIT BIDIRECTIONAL DATA BUS
BUS 0 BUS 1 BUS 2 BUS 3 BUS 4 BUS 5 BUS 6 BUS 7
X (4)
T (8)
P (4)
I (4)
N (4)
N0 N1 N2
I/O COMMANDS
CDP1805AC, CDP1806AC
Absolute Maximum Ratings
DC Supply Voltage Range, (VDD) (All Voltages Referenced to VSS Terminal). . . . . . . . . -0.5V to +7V Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V DC Input Current, any One Input . . . . . . . . . . . . . . . . . . . . . . . . . ±10mA
Thermal Information
Thermal Resistance (Typical, Note 2) JA (oC/W) JC (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . 50 N/A PLCC Package . . . . . . . . . . . . . . . . . . 46 N/A SBDIP Package. . . . . . . . . . . . . . . . . . 55 15 Device Dissipation Per Output Transistor TA = Full Package Temperature Range . . . . . . . . . . . . . . 100mW Operating Temperature Range (TA) Package Type D . . . . . . . . . . . . . . . . . . . . . . . . .-55oC to +125oC Package Type E and Q . . . . . . . . . . . . . . . . . . . . .-40oC to +85oC Storage Temperature Range (TSTG) . . . . . . . . . . . .-65oC to +150oC Lead Temperature (During Soldering) At Distance 1/16 ±1/32in (1.59 ± 0.79mm) from case for 10s Max . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +265oC Printed Circuit Board Mount: 57mm x 57mm Minimum Area x 1.6mm Thick G10 Epoxy Glass, or Equivalent.
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Recommended Operating Conditions
TA = Full-Package Temperature Range. For maximum reliability, operating conditions
should be selected so that operation is always within the following ranges. TEST CONDITIONS VDD (V ) 5 CDP1805ACD, CDP1805ACE CDP1806ACD, CDP1806ACE M IN 4 VSS 3. 2 MA X 6.5 VDD UNITS V V µs
PARAMETER DC Operating Voltage Range Input Voltage Range Minimum Instruction Time (Note 1) (fCL = 5MHz) Maximum DMA Transfer Rate Maximum Clock Input Frequency, Load Capacitance (CL) = 50pF Maximum External Counter/Timer Clock Input Frequency to EF1, EF2 NOTES:
5 5
DC
0.625 5
Mbyte/s M Hz
5
DC
2
M Hz
1. Equals 2 machine cycles - one Fetch and one Execute operation for all instructions except Long Branch, Long Skip, NOP, and "68" family instructions, which are more than two cycles. 2. JA is measured with the component mounted on an evaluation PC board in free air.
Static Electrical Specifications
at TA = -40oC to +85oC, VDD ±5%, Except as Noted CDP1805ACD, CDP1805ACE CDP1806ACD, CDP1806ACE VO (V) 0.4 0.4 4.6 4.6 VIN (V) 0, 5 0, 5 5 0, 5 0 0, 5 0, 5 VDD (V) 5 5 5 5 5 5 5 (NOTE 3) TYP 50 4 0. 4 -4 -0 . 2 0 5
PARAMETER Quiescent Device Current, IDD Output Low Drive (Sink) Current, (Except XTAL), IOL XTAL Output, IOL Output High Drive (Source) Current (Except XTAL, IOH XTAL, IOH Output Voltage Low Level, VOL Output Voltage High Level, VOH
MIN 1. 6 0. 2 -1 . 6 -0 . 1 4. 9
MA X 200 0.1 -
UNITS µA mA mA mA mA V V
4
CDP1805AC, CDP1806AC
Static Electrical Specifications
at TA = -40oC to +85oC, VDD ±5%, Except as Noted (Continued) CDP1805ACD, CDP1805ACE CDP1806ACD, CDP1806ACE VO (V) 0.5, 4.5 0.5, 4.5 VIN (V) VDD (V) 5 5 (NOTE 3) TYP -
PARAMETER Input Low Voltage (BUS0 - BUS7, ME), VIL Input High Voltage (BUS0 - BUS7, ME), VIH Schmitt Trigger Input Voltage (Except BUS0 - BUS7, ME) Positive Trigger Threshold, VP Negative Trigger Threshold, VN Hysteresis, VH Input Leakage Current, IIN Three-State Output Leakage Current, IOUT Input Capacitance, CIN Output Capacitance, COUT Total Power Dissipation (Note 4) Run Idle "00" at M (0000) Minimum Data Retention Voltage, VDR Data Retention Current, IDR NOTES: 3. Typical values are for TA = +25oC and nominal VDD. 4. External clock: f = 5MHz, t R, t F = 10ns; C L = 50pF.
MIN 3. 5
MA X 1.5 -
UNITS V V
0.5, 4.5 0.5, 4.5 0.5, 4.5 0, 5 -
0, 5 0, 5 -
5 5 5 5 5 -
2. 2 0. 9 0. 3 -
2. 9 1. 9 0. 9 ± 0. 1 ± 0. 2 5 10
3.6 2.8 1.6 ±5 ±5 7.5 15
V V V µA µA pF pF
-
VDD = VDR VDD = 2.4
5 5
-
35 12 2 25
50 18 2.4 100
mW mW V µA
Dynamic Electrical Specifications
at TA = -40o to +85oC; C L = 50pF; Input t R, t F = 10ns; Input Pulse Levels = 0.1V to V DD -0.1V; V DD = 5V, ±5%. CDP1805AC CDP1806AC (NOTE 5) TYP
PARAMETER Propagation Delay Times Clock to TPA, TPB, tPLH, tPHL Clock-to-Memory High-Address Byte, tPLH, tPHL Clock-to-Memory Low-Address Byte, tPLH, tPHL Clock to MRD, tPLH, tPHL Clock to MWR, tPLH, tPHL (See Note 5) Clock to (CPU DATA to BUS), tPLH, tPHL Clock to State Code, tPLH, tPHL Clock to Q, tPLH, tPHL Clock to N, tPLH, tPHL Clock to Internal RAM Data to BUS, tPLH, tPHL
MA X
UNITS
150 325 275 200 150 375 225 250 250 420
275 550 450 325 275 625 400 425 425 650
ns ns ns ns ns ns ns ns ns ns
5
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