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Part: CDP1823C/3
Category:
Memory
-> SRAM
-> SRAM
Description: High-reliability CMOS 128-Word X 8-Bit Static RAM
Company: Intersil Corporation
Datasheet: Download CDP1823C/3 datasheet File size : 31 kB
Request For quote: Find where to buy CDP1823C/3
Datasheet text preview:
TM
CDP1823C/3
High-Reliability CMOS 128-Word x 8-Bit Static RAM
to 2V at 25oC · Latch-Up-Free Transient Radiation Tolerance
March 1997
Features
· For Applications in Aerospace, Military, and Critical Industrial Equipment · Compatible with CDP1800-Series Microprocessors at Maximum Speed · Interfaces with CDP1800-Series without Additional Components · Fast Access Time · At VDD = 5V, +25oC . . . . . . . . . . . . . . . . . . . . . . . . 275ns · Single Voltage Supply · Common Data Inputs and Outputs · Multiple Chip Select Inputs to Simplify Memory System Expansion · High Noise Immunity . . . . . . . . . . . . . . . . . . 30% of VDD · Memory Retention for Standby Battery Voltage Down Microprocessors
Ordering Information
PACKAGE SBDIP TEMP. RANGE PART NUMBER (5 V) P KG. NO. D24.6
-55oC to +125oC CDP1823CD3
Description
The CDP1823C/3 is a 128 word x 8-bit CMOS/SOS static random access memory. It is compatible with the CDP1802, CDP1804, CDP1805, and CDP1806 microprocessors, and will interface directly without additional components. The CDP1823C has a recommended operating voltage range of 4V to 6.5V.
Pinout
CDP1823C/3 (SBDIP) TOP VIEW
BUS 0 1 BUS 1 2 BUS 2 3 BUS 3 4 BUS 4 5 BUS 5 6 BUS 6 7 BUS 7 8 CS 1 9 CS2 10 CS3 11 VSS 12 24 VDD 23 A0 22 A1 21 A2 20 A3 19 A4 18 A5 17 A6 16 MWR 15 MRD 14 CS5 13 CS4
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2001. All Rights Reserved
File Number
2982.1
31
CDP1823C/3
OPERATIONAL MODES FUNCTION Re a d Write S tandby Not Selected MRD 0 1 1 X X X X X MW R X 0 1 X X X X X CS1 1 1 1 0 X X X X CS2 0 0 0 X 1 X X X CS3 0 0 0 X X 1 X X CS4 1 1 1 X X X 0 X CS5 0 0 0 X X X X 1 BUS TERMINAL STATE Stor age State of Addressed Word Input High Impedance H igh Impedance H igh Impedance
NOTE: 1. Logic 1 = High, Logic 0 = Low, X = Don't Care.
32
CDP1823C/3
Absolute Maximum Ratings
DC Supply Voltage Range, (V DD) (All Voltages Referenced to VSS Terminal) CDP1823C/3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . . ±10mA
Thermal Information
Thermal Resistance (Typical) JA ( oC/W) JC (oC/W) SBDIP Package. . . . . . . . . . . . . . . . . . 60 17 Maximum Operating Temperature Range (TA) . . . .-55oC to +125oC Maximum Storage Temperature Range (TSTG) . . .-65oC to +150oC Maximum Lead Temperature (During Soldering) . . . . . . . . . +265oC Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . +150oC
Recommended Operating Conditions
At TA = Full Package Temperature Range. For maximum reliability, operating conditions should be selected so that operation is always within the following ranges: LIMITS
P ARAMETER Supply Voltage Range Recommended Input Voltage Range
MIN 4 V SS
M AX 6.5 V DD
UNITS V V
Static Electrical Specifications
VDD = 5V ±5% CONDITIONS VO (V) IDD IOL IOH V OL V OH V IL V IH IIN IDD1 IOUT C IN C OUT 0.4 4.6 0.5, 4.5 0.5, 4.5 0, 5 VIN (V) 0, 5 0, 5 0, 5 0, 5 0, 5 0, 5 0, 5 0, 5 VDD (V) 5 5 5 5 5 5 5 5 5 5 -55oC, +25oC MIN 2.7 VDD - 0.1 0.7 V DD M AX 270 -1.3 0.1 0.3 VDD ±2.6 5 ±2.6 7.5 15 LIMITS +125oC MIN 1.5 VDD - 0.1 0.7 VDD M AX 1000 -0.7 0.1 0.3 VDD ± 10 10 ± 10 7.5 15 UNITS µA mA mA V V V V µA mA µA pF pF
PARAMETER Quiescent Device Current (Note 1) Output Low (Sink) Current (Note 1) Output High (Source) Current (Note 1) Output Voltage Low-Level Output Voltage High-Level Input Low Voltage Input High Voltage Input Leakage Current (Note 1) Operating Current (Note 1) Three-S tate Output Leakage Current Input Capacitance Output Capacitance NOTE:
1. Limits designate 100% testing, all other limits are designer's parameters under given test conditions and do not represent 100% testing.
Read Cycle Dynamic Electrical Specifications tR, tF = 10ns, CL = 50pF
LIMITS +25oC, -55oC PARAMETER Read Cycle Access Time from Address Change (Note 1) Access Time from Chip Select SYMBOL tRC tAA tAC VDD (V) 5 5 5 MIN 360 M AX 360 360 +125oC MIN 505 M AX 505 505 UNITS ns ns ns
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CDP1823C/3
Read Cycle Dynamic Electrical Specifications tR, tF = 10ns, CL = 50pF (Continued)
LIMITS +25oC, -55oC P ARAME TER Access Time from MRD (Note 1) Data Hold Time After Read NOTE: 1. Limits designate 100% testing. All other limits are designer's parameters under given test conditions and do not represent 100% testing. SYMBOL tAM tDH VDD (V) 5 5 MIN 50 M AX 310 +125oC MIN 70 M AX 435 UNITS ns ns
t RC t AA AD DRESS t AM (NOTE 1)
MRD
CS2, CS3, CS5 (NOTE 1) tAC CS1, CS4 t DH 90% HIGH IMPEDANCE VALID DATA 10%
NOTES : 1. Minimum timing for valid data output. Longer times will initiate an earlier but invalid output. 2. MWR is high during read operation. Timing measurement reference is 0.5VDD. FIGURE 1. READ CYCLE TIMING DIAGRAM
Write Cycle Dynamic Electrical Specifications tR, tF = 10ns, CL = 50pF
LIMITS +25oC, -55oC VDD (V) 5 5 5 5 5 (NOTE 2) MIN 280 70 70 140 70 +125oC (NOTE 2) MIN 400 100 100 200 100
PARAMETER Write Cycle Address Setup Time (Note 1) Address Hold Time Write Pulse Width (Note 1) Data to MWR Setup Time (Note 1)
SYMBOL tWC tAS tAH tWW tDS
M AX -
M AX -
UNITS ns ns ns ns ns
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CDP1823C/3
Write Cycle Dynamic Electrical Specifications tR, tF = 10ns, CL = 50pF (Continued)
LIMITS +25oC, -55oC VDD (V) 5 5 (NOTE 2) MIN 50 210 +125oC (NOTE 2) MIN 70 300
PA RAMETER Data Hold Time from MWR (Note 1) Chip Select Setup NOTES :
SYMBOL tDH tCS
M AX -
M AX -
UNITS ns ns
1. Limits designate 100% testing. All other limits are designer's parameters under given test conditions and do not represent 100% testing. 2. Minimum timing to allow the indicated function to occur.
tWC t AS ADDRESS tAH C S1, CS4 t CS CS2, CS3, CS5
MWR
tW W tDS t DH
BUS 0-7
VALID DATA
NOTE: 1. MRD must be high during write operation. FIGURE 2. WRITE CYCLE TIMING WAVEFORMS
Data Retention Specifications
TEST CONDITIONS VDR (V) 2 VDD (V) 5 5 +25oC, -55oC MIN 450 450 M AX 2 100 LIMITS +125oC MIN 650 650 M AX 2.5 400 UNITS V µA ns ns
PA RAME TER Minimum Data Retention Voltage (Note 1) Data Retention Quiescent Current Chip Deselect to Data Retention Time Recovery to Normal Operation Time NOTE:
SYMBOL VDR IDD t CDR tRC
1. Limits designate 100% testing. All other limits are designer's parameters under given test conditions and do not represent 100% testing.
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