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Part: DG405DY
Category:
Analog & Mixed-Signal Processing
-> Switches & Multiplexers
-> Analog Switches
Description:
Company: Intersil Corporation
Datasheet: Download DG405DY datasheet File size : 304 kB
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®
DG401, DG403, DG405
Da ta Sheet N ov e m be r 2002 FN 3 2 84 . 7
Monolithic CMOS Analog Switches
The DG401, DG403 and DG405 monolithic CMOS analog switches have TTL and CMOS compatible digital inputs. These switches feature low analog ON resistance (<45) and fast switch time (tON < 150ns). Low charge injection simplifies sample and hold applications. The improvements in the DG401/403/405 series are made possible by using a high voltage silicon-gate process. An epitaxial layer prevents the latch-up associated with older CMOS technologies. The 44V maximum voltage range permits controlling 30VP-P signals. Power supplies may be single-ended from +5V to +34V, or split from ±5V to ±17V. The analog switches are bilateral, equally matched for AC or bidirectional signals. The ON resistance variation with analog signals is quite low over a ±15V analog input range. The three different devices provide the equivalent of two SPST (DG401), two SPDT (DG403) or two DPST (DG405) relay switch contacts with CMOS or TTL level activation. The pinout is similar, permitting a standard layout to be used, choosing the switch function as needed.
Features
· ON Resistance (Max). . . . . . . . . . . . . . . . . . . . . . . . . 45 · Low Power Consumption (PD) . . . . . . . . . . . . . . . . . . .<35µW · Fast Switching Action - tON (Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150ns - tOFF (Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100ns · Low Charge Injection · DG401 Dual SPST; Same Pinout as HI-5041 · DG403 Dual SPDT; DG190, IH5043, IH5151, HI-5051 · DG405 Dual DPST; DG184, HI-5045, IH5145 · TTL, CMOS Compatible · Single or Split Supply Operation
Applications
· Audio Switching · Battery Operated Systems · Data Acquisition · Hi-Rel Systems
Pinout
DG401 (SOIC) TOP VIEW
D1 1 NC 2 NC 3 NC 4 NC 5 NC 6 NC 7 D2 8 16 S1 15 IN1 14 V13 GND 12 VL 11 V+ 10 IN2 9 S2
· Sample and Hold Circuits · Communication Systems · Automatic Test Equipment
Ordering Information
PART NUMBER DG401DY DG403DJ DG403DY TEMP. RANGE (o C ) -40 to 85 -40 to 85 -40 to 85 -40 to 85 PACKAGE 16 Ld SOIC 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC PKG. NO. M16. 15 E16. 3 M16. 15 M16. 15
DG403 (PDIP, SOIC) DG405 (SOIC) TOP VIEW
D1 1 NC 2 D3 3 S3 4 S4 5 D4 6 NC 7 D2 8 16 S1 15 IN1 14 V13 GND 12 VL 11 V+ 10 IN2 9 S2
DG405DY
TRUTH TABLE DG 401 LOGIC 0 1 NOTE: SWITCH OFF ON DG 403 SWITCH 1, 2 SWITCH 3, 4 OFF ON ON OFF DG 405 SWITCH OFF ON
Logic "0" 0.8V. Logic "1" 2.4V.
NOTE: (NC) No Connection.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved
Functional Diagrams
DG 401
VL 12 S1 16 V+ 11 1 D1 S1 S3 IN1 15 IN2 S2 10 9 8 16 4 VL 12
DG 403
V+ 11 1 3 D1 D3 S1 S3 16 4 VL
DG 405
V+ 11 1 3 D1 D3
12
IN1 15 IN2 D2 S2 S4 13 GND 14 V10 9 5 13 GND 14 V8 6
IN1 15 IN2 D2 D4 S2 S4 10 9 5 13 GND 14 V8 6
D2 D4
SWITCHES SHOWN FOR LOGIC "1" INPUT
Schematic Diagram
V+ SOURCE
VL
V-
VIN V+ G ND V-
DRAIN
2
Absolute Maximum Ratings
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44.0V GND to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25V VL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (GND - 0.3V) to (V+) +0.3V Digital Inputs VS , VD (Note 1) . . . . . (V-) -2V to (V+) + 2V or 30mA, Whichever Occurs First Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . 30mA Peak Current, S or D (Pulsed 1ms, 10% Duty Cycle, Max) . . 100mA
Thermal Information
Thermal Resistance (Typical, Note 2) JA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range. . . . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20V (Max) Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8V (Max) Input High Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4V (Min) Input Rise and Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20ns
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. Signals on SX , DX , or INX exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings. 2. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
Test Conditions: V+ = +15V, V- = -15V, VIN = 2.4V, 0.8V (Note 3), VL = 5V, Unless Otherwise Specified TEST CONDITIONS RL = 300, CL = 35pF RL = 300, CL = 35pF CL = 10nF, VG = 0V, RG = 0 RL = 100, CL = 5pF, f = 1MHz f = 1MHz, VS = VD = 0V (Figure 7) TEMP (oC) 25 25 25 25 25 25 25 25 25 VIN Under Test = 0.8V, All Others = 2.4V VIN Under Test = 2.4V, All Others = 0.8V F ull F ull F ull V+ = 13.5V, V- = -13.5V, IS = 10mA, VD = ±10V 25 F ull 25 F ull 25 F ull 25 F ull V± = ±16.5V, VD = VS = ±15.5V 25 F ull (NOTE 4) MI N 5 -1 -1 -1 5 -0.5 -5 -0.5 -5 -1 -1 0 (NOTE 5) TYP 100 60 12 60 72 -9 0 12 12 39 0.005 0.005 20 3 -0 . 0 1 -0 . 0 1 -0. 04 (NOTE 4) MAX 150 100 1 1 15 45 55 3 5 0.5 5 0.5 5 1 10 UNITS ns ns ns pC dB dB pF pF pF µA µA V nA nA nA nA nA nA
PARAMETER DYNAMIC CHARACTERISTICS Turn-ON Time, tON Turn-OFF Time, tOFF Break-Before-Make Time Delay (DG403), tD Charge Injection, Q (Figure 3) OFF Isolation (Figure 4) Crosstalk (Channel-to-Channel) (Figure 6) Source OFF Capacitance, CS(OFF) Drain OFF Capacitance, CD(OFF) Channel ON Capacitance, CD(ON) + CS(ON) DIGITAL INPUT CHARACTERISTICS Input Current with VIN Low, IIL Input Current with VIN High, IIH ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG Drain-Source ON Resistance, rDS(ON)
rDS(ON) Matching Between Channels, rDS(ON) V+ = 16.5V, V- = -16.5V, IS = -10mA, VD = 5, 0, -5V Source OFF Leakage Current, IS(OFF) Drain OFF Leakage Current, ID(OFF) Channel ON Leakage Current, ID(ON) + IS(ON) V+ = 16.5V, V- = -16.5 VD = ±15.5V, VS = 15.5V
3
Electrical Specifications
Test Conditions: V+ = +15V, V- = -15V, VIN = 2.4V, 0.8V (Note 3), VL = 5V, Unless Otherwise Specified (Continued) TEST CONDITIONS V+ = 16.5V, V- = -16.5V, VIN = 0V or 5V TEMP (oC) 25 F ull 25 F ull 25 F ull 25 F ull (NOTE 4) MI N -1 -5 -1 -5 (NOTE 5) TYP 0. 01 -0. 0 1 0. 01 -0. 0 1 (NOTE 4) MAX 1 5 1 5 UNITS µA µA µA µA µA µA µA µA
PARAMETER POWER SUPPLY CHARACTERISTICS Positive Supply Current, I+ Negative Supply Current, ILogic Supply Current, IL Ground Current, IGND NOTES:
3. VIN = input voltage to perform proper function. 4. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 5. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
Test Circuits and Waveforms
3V LOGIC INPUT 50% 0V tOFF SWITCH INPUT SWITCH OUT P UT VS VO 0V tON SWITCH INPUT -VS (NOTE 7) 10% 0V -15V 90% 90% LOGIC I NP UT GND VSWITCH I NP UT S1 IN1 RL CL tr < 20ns tf < 20ns 5V VL +15V V+ RL = 300 CL = 35pF D1 VO
NOTES: 6. Logic input waveform is inverted for switches that have the opposite logic sense. 7. VS = 10V for tON , VS = -10V for tOFF . FIGURE 1A. MEASUREMENT POINTS
Repeat test for IN2 and S2. For load conditions, see Specifications. CL includes fixture and stray capacitance. RL V O = V S ----------------------------------RL + rD S ( O N ) FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
3V LOGIC INPUT 0V VS1 SWITCH OUT P UT (VO1) 90% 0V VS2 90% 0V tD tD VS1 = 10V VS2 = 10V IN1 LOGIC I NP UT
5V VL
+15V V+
RL = 300 CL = 35pF D1 D2 VO2 RL 1 VO 1 CL 1
RL 2 GND 0V V-15V
CL 2
SWITCH OUT P UT (VO2)
CL includes fixture and stray capacitance. FIGURE 2B. TEST CIRCUIT
FIGURE 2A. MEASUREMENT POINTS FIGURE 2. BREAK-BEFORE-MAKE TIME
4
Test Circuits and Waveforms
(Continued)
5V VL +15V V+ D1 VO
SWITCH OUT P UT VO
VO
RG
INX
ON
OFF
ON
VG
CL GND V-15V
Q = VO x CL 0V
FIGURE 3A. MEASUREMENT POINTS FIGURE 3. CHARGE INJECTION
FIGURE 3B. TEST CIRCUIT
C SI GNAL GENERATOR
V+
+15V
+5 V
VL
C SIG NAL GENERATOR
C
V+
+15V
+5 V
VL
C
VS
VS
INX
0V , 2.4V
INX
0V , 2.4V
ANALYZER RL
VD V-15V C
ANALYZER GND RL
VD V-15V C
GND
FIGURE 4. OFF ISOLATION TEST CIRCUIT
FIGURE 5. INSERTION LOSS TEST CIRCUIT
C SIG NAL GENERATOR
V+
+15V
+5 V
VL
C C V+
+15V
+5V
VL
C
VS1
VD1
50 VS
0V, 2.4V
IN1
IN2
0V, 2.4V
INX IMPEDANCE ANALYZER VD
0V , 2.4V AS REQUIRED
ANALYZER RL
VD2
VS2 V-15V C
NC
GND
GND
V-15V
C
FIGURE 6. CROSSTALK TEST CIRCUIT
FIGURE 7. CAPACITANCES TEST CIRCUIT
5
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