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Part: EL4511
Category:
Description: Video SYNC Separator, DTV HDTV And Projector, Tri-level & Bi-level Auto Sync, 150kHz Line Rate, 3.3V And 5V
Company: Intersil Corporation
Datasheet: Download EL4511 datasheet File size : 7 kB
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EL4511
D a t a Sheet Ju n e 4, 2003 FN7009.3
PRELIMINARY
Super Sync Separator
The EL4511 sync separator IC is designed for operation in the next generation of DTV, HDTV, and projector applications, as well as broadcast equipment and other applications where video signals need to be processed. The EL4511 accepts sync on green, separate sync, and H/V sync inputs, automatically selecting the relevant format. It is also capable of detecting and decoding tri-level syncs used with the latest HD systems. Unlike standard sync separators, the EL4511 can automatically detect the line rate and locks to it, without the use of an external RSET resistor. The EL4511 is available in a 24-pin QSOP package and operates over the full 0°C to 70°C temperature range.
Features
· Composite, component, HDTV, and PC signal-compatible · Tri-level & bi-level sync-compatible · Auto sync detection · 150kHz max line rate · Low power · Small package outline · 3.3V and 5V operation
Applications
· HDTV/DTV analog inputs · Video projectors · Computer monitors · Set top boxes
Ordering Information
PART NUMBER EL4511C U EL4511C U-T 7 EL4511C U-T 1 3 PACKAGE 24-Pin QSOP 24-Pin QSOP 24-Pin QSOP TAPE & REEL 7" 13" PKG. DWG. # MDP0040 MDP0040 MDP0040
· Security video · Broadcast video equipment
Pinout
EL4511 (24-PIN QSOP) TOP VIEW
XTAL 1 VBLANK 2 SYNCLOCK 3 PDWN 4 SDENB 5 SCL 6 SDA 7 GNDD 1 8 HIN 9 SYNCIN 1 0 VERTIN 11 LEVEL 1 2 2 4 XTALN 23 ODD/EVEN 22 VERTOUT 2 1 HOUT 20 BACKPORCH 19 SYNCOUT 1 8 VCCD 1 7 GNDD2 1 6 GNDA2 1 5 VCCA2 1 4 VCCA1 1 3 GNDA1
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003. All Rights Reserved. Elantec is a registered trademark of Elantec Semiconductor, Inc. All other trademarks mentioned are the property of their respective owners. Manufactured under U.S. Patent 5,528,303 Manufactured under License, U.S. Patents 5,486,869; 5,754,250
EL4511
Absolute Maximum Ratings (TA = 25°C)
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . (VS to GND) +6V Pin Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V, VS +0.3V VCCA1, VCCA2 & VCCD . . . . . . . . . . . . . . . .Must Be Same Voltage Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 125°C Ambient Operating Temperature . . . . . . . . . . . . . . . . . 0°C to +70°C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER GENERAL ISD
VS = VCCA1 = VCCA2 = VCCD = +5V, TA = 25°C, NTSC input signal on SYNCIN, no output loads, unless otherwise specified. CONDITIONS MIN TYP MAX UNIT
DESCRIPTION
Digital Supply Current
(Note 1) Standby PDWN = VCCD (Note 2)
15 4 3 2.5 3 3
20 20 20 20 20 20
mA µA mA µA mA µA
ISA2
Rate Acquisition Oscillator Supply Current Analog Processing Supply Current
(Note 1) Standby PDWN = VCCD (Note 1) Standby PDWN = VCCD (Note 2)
ISA1
COMPOSITE SYNC INPUT AT SYNCIN VSYNC VSLICE Sync Signal Amplitude Slicing Level of Sync Signal AC coupled to SYNCIN pin (Notes 1 & 3) After sync lock is attained, see description 140 50 600 mV %
HORIZONTAL AND VERTICAL INPUT AT HIN, VERTIN HSLICE, VSLICE Slice Level of HIN and VERTIN THINL FHINH TVINL FVINH H Sync Width H Sync Frequency V Sync Width V Sync Frequency 3 10.75 2 23 1.4 12 .8 150 7 100 V % of H time kHz H lines Hz
LOGIC OUTPUT SIGNALS, HOUT, VOUT, VBLANK, BACKPORCH, ODD/EVEN, SYNCLOCK O/PLOW Logic Low State 1.6mA, VCCD = 5V 1.6mA, VCCD = 3.3V O/PHI Logic High State 1.6mA, VCCD = 5V 1.6mA, VCCD = 3.3V TdHOUT TdSYNCOUT TdBACKPORCH HOUT Timing Relative to Input See timing diagrams 1, 2, 3 & 4 VCCD-0.4 VCCD-0.5 GNDD+0.4 GNDD+0.5 V V
SYNCOUT Timing Relative to Input See timing diagrams 1, 2, 3 & 4 BACKPORCH Timing Relative to Input See timing diagrams 1, 2, 3 & 4
LEVEL OUTPUT DRIVER, LEVEL VLEVEL ZLEVEL 2 X Amplitude of VSYNC O/P Resistance of Driver Stage Refer to description of operation 1.9x 2 . 15x 450 2.4x
REFERENCE OSCILLATOR FIN FXTAL Reference Input Frequency Crystal Frequency Refer to description of operation Watch crystal (optional) 32.768 50 kHz kHz
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EL4511
Electrical Specifications
PA RAMETER VS = VCCA1 = VCCA2 = VCCD = +5V, TA = 25°C, NTSC input signal on SYNCIN, no output loads, unless otherwise specified. (Continued) CONDITIONS M IN TYP M AX UN IT
DESC RIPTION
CONTROL INTERFACE SIGNALS PDWN, SDENB, SCL AND SDA VHIGH VLOW O/PVHI O/PVLOW FSCL TCLS TCLH TLC TDC TCD NOTES: 1. NTSC signal; see curves for other rates 2. XTAL pin must be low, otherwise 70µA 3. I/P range reduces if VS of 3.3V - 4.5V (see timing diagram 1) Input Logic High Threshold Input Logic Low Threshold SDA O/P Logic High State SDA O/P Logic Low State Serial Control Clock Frequency Setup Time Hold Time Load to Clock Time Hold to Clock Time Clock to Data Out Time @ 1mA @ 1mA 5 30 30 30 30 30 VGNDD+1V VCCD-0.4 GNDD+0.4 V V MHz ns ns ns ns ns VCCD-1V
Pin Descriptions
PIN NUMBER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 PIN NAME XTAL VBLANK SYNCLOCK PWDN SDENB SCL SDA GNDD1 HIN SYNCIN VERTIN LEVEL GNDA1 VCCA1 VCCA2 GNDA2 GNDD2 VC CD1 SYNCOUT BACKPORCH HOUT VERTOUT ODD/EVEN XTALN PIN TYPE Input Logic Output Logic Output Logic Input Logic Input Logic Input Logic BIDIR Power Input Input Input Output Power Power Power Power Power Power Logic Output Logic Output Logic Output Logic Output Logic Output Output PIN DESCRIPTION Crystal input (see Table 5 for details) Vertical blank output Indicates that the EL4511 has locked to the line rate and has found three consecutive "good H lines" Power-down = hi Serial interface enable = low Serial clock Serial data (input for chip setup, output for diagnostic information) Digital ground 1 Horizontal sync Video input, which may incorporate sync signal; connect to Y or G Vertical sync input Indicates 2x amplitude of sync tip vs. back porch; referred to ground Analog ground 1 Analog power supply 1 Analog power supply 2 Analog ground 2 Digital ground 2 Digital power supply 1 Composite sync output Back porch output Horizontal sync output Vertical sync output Odd-Even field indicator output Crystal output (see Table 5 for details)
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EL4511
TABLE 1. SERIAL INTERFACE REGISTER BIT ALLOCATIONS REGISTER REGISTER NUMBER BIT 1 7 6 5:3 2 5 4 1 3 7 6:0 4 7:4 3 2 1 0 6 7:6 7 7:0 8 7:4 3 2 1 0 9 6 5 4 3 2 1 0 13 7:0 14 SIGNAL NAME General Control Reg 1 General Reset A lwaysEnOutp uts M odeCtr l General Control Reg 2 Select Fixed Slicing (no S/H) FILTER_ENABLED OE_MODE VBLANK Control Reg 1 EnVBlank VSTPlusBP VBLANK & Polarity Ctrl VFrontPorch DefaultHPolarity DefaultVPolarity EnHPolarityDet EnVPolarityDet Oscillator Control 2 CMuxCtrl VBLANK O/P Reg 1 LinesPerFrame VBLANK O/P Reg 2 & Misc LinesPerFrame En50Slice LP F V a l i d progressive tri-level detect Analog Control Reg 1 E NXTAL ENLEVELBLANKING ENLEVEL E NSYCLAMP ENALOS ENRVIDEO PWRSAVE Absolute Timing Ref 1 CountsPerField Absolute Timing Ref 2 & Misc R R Crystal clock periods per field: L.S. Byte. (see description) R/W 0 0 0 0 0 0 0 Set Hi to enable crystal oscillator. Set Hi to enable VLEVEL when not locked. Set Hi to disable VLEVEL output. Set Hi to disable "soft" sync tip clamping in SYNCIN. Set Hi to disable analog loss of signal feature. Set Hi to disable internal biasing on SYNCIN (passive resistor or soft clamp.) Set Hi to put the analog circuit into powersave mode. R R 80h Most significant 4 bits of lines per frame count. Indicates sample and hold front end is being used. Indicates lines per frame has been updated. Not valid for certain types of composite sync. Only valid if tri-level sync detected. R/W R/W R/W R/W T YPE R/W RESET VALUE 00h 0 0 0 10h 0 1 0 90h 1 10h 4F h 4h 1 1 1 1 22h 0 Multiplexes clock onto VBLANK or Odd/Even. See Table 3. Only valid if VBLANK circuit is enabled Least significant byte of lines per frame count. Number of lines before vertical sync time. HIN polarity on reset if EnHpolarityDet = Lo. VERTIN polarity on reset and if EnVpolarityDet = Lo. Allows EL4511 to detect and set polarity on HIN. Allows EL4511 to detect and set polarity on VERTIN. Enables vertical blank interval detection algorithm. Number of lines after vertical sync time. Necessary for SECAM. May be useful for VCRs. Set Hi to include digital filter on horizontal input. Set Hi for Odd/Even changes on rising edge of vertical. Software reset. Does not affect serial interface. Overrides internal qualification of outputs. Sync acquisition. Selects input signal. See Table 2. DESCRIPTION AND COMMENTS
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EL4511
TABLE 1. SERIAL INTERFACE REGISTER BIT ALLOCATIONS (Continued) REGISTER REGISTER NUMBER BIT 7:6 5 4 3 2 1 0 16 4 3 SIGNAL NAME CountsPerField S yncLock CPFValid S etBiLevel V i n S y n c D et V inPolarity HPolarity Oscillator Settings Observe 2 RateLocked A LOS R Indicates line rate successfully acquired. Analog loss of signal, measured via S/H. H indicates analog signal amplitude is below threshold. T YPE RESET VALUE DESCRIPTION AND COMMENTS Crystal clock periods per field: Bits 9:8. (see description) As sync lock pin. Counts per field valid. Set L if read occurs during an update. Lo: Tri-level mode; Hi: Bi-level mode. Indicates vertical sync on VERTIN successfully acquired. VERTIN polarity setting: Observe. HIN polarity setting: Observe.
VCCA1
VCCD
LEVEL VERTICAL SYNC COMPOSITE SYNC HORIZONTAL SYNC VERTIN SYNCIN HIN SLICING & ANALOG PROCESSING DIGITAL PROCESSING HOUT SYNCOUT VERTOUT VBLANK BACKPORCH POWER DOWN PDWN RESET ODD/EVEN SYNCLOCK LOW ACTIVE SERIAL DATA ENABLE SERIAL CLOCK SERIAL DATA SDENB SCL SDA SERIAL I/F
SYNC LEVEL HORIZONTAL O/P COMP SYNC O/P VERTICAL O/P VERTICAL BLANKING O/P BACK PORCH O/P ODD/EVEN O/P SYNC LOCK O/P
RATE ACQUISITION OSCILLATOR
REFERENCE OSCILLATOR
GNDD1 GNDD2
GNDA 1
VCCA2
GNDA2
XTALIN
XTAL
MODE CONTROL PINS
FIGURE 1. BLOCK DIAGRAM
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