Details, datasheet, quote on part number: HA456CM
PartHA456CM
CategoryCommunication => Network => Switches => Digital Crosspoint Switches
TitleMultiplexers
Description120MHz, Low Power, 8 X 8 Video Crosspoint Switch
CompanyIntersil Corporation
DatasheetDownload HA456CM datasheet
Cross ref.Similar parts: DG884, MAX4456CQH, MAX4456EQH, MAX456CHQ
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Features, Applications

The HA456 is the first x 8 video crosspoint switch suitable for high performance video systems. Its high level of integration significantly reduces component count, board space, and cost. The crosspoint switch contains a digitally controlled matrix of 64 fully buffered switches that connect eight video input signals to any, or all, matrix outputs. Each matrix output connects to an internal, high-speed (200V/µs), unity gain buffer capable of driving 400 and to ±2V. For applications requiring gain or increased drive capability, the HA456 outputs can be connected directly to two HFA1412 quad, gain of two video buffers, which are capable of driving 75 loads. This crosspoint's true high impedance three-state output capability, makes it feasible to parallel multiple HA456s and form larger switch matrices.

Features

Fully Buffered Inputs and Outputs (AV = +1) Routes Any Input Channel to Any Output Channel Switches Standard and High Resolution Video Signals Serial or Parallel Digital Interface Expandable for Larger Switch Matrices Wide Bandwidth. 120MHz High Slew Rate. 200V/µs Differential Gain and Phase. 0.05%, 0.05 Degrees Low Crosstalk 10MHz. -55dB

Applications
Professional Video Switching and Routing Security and Video Editing Systems
TEMP. PART NUMBER RANGE (oC) to 70 PACKAGE 44 Ld PLCC PKG. DWG. # N44.65

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.

NAME NC D1/ SER OUT No connect. Not internally connected. Parallel Data Bit input D1 for Parallel Programming Mode. Serial Data Output (MSB of shift register) for cascading multiple HA456s in serial programming mode. Simply connect Serial Data Out of one HA456 to Serial Data In of another HA456 to daisy chain multiple devices. Parallel Data Bit Input D0 for Parallel Programming Mode. Serial Data Input (input to shift register) for serial programming mode. Output Channel Address Bits. These inputs select the output being programmed in parallel programming mode. Analog Video Input Lines. Digital Ground. Connect both DGND pins to AGND. A user strapped input that defines whether synchronous channel switching is edge or level controlled. With this pin strapped high, the slave register loads from the master register (thus changing the switch matrix state) on the rising edge of the LATCH signal. it is strapped low (level mode), the slave register is transparent while LATCH is low, passing data directly from the master register to the switch state decoders. Strapping EDGE/LEVEL and LATCH low causes the channel switch to execute on the WR rising edge (not recommended for serial mode operation). Positive Supply Voltage. Connect all V+ pins together and decouple each pin to AGND (Figure 2). A user strapped input that defines whether the serial (SER/PAR 1) or parallel (SER/PAR = 0) digital programming interface is being utilized. Negative Supply Voltage. Connect both V- pins together and decouple each pin to AGND (Figure 2). WRITE Input. In serial mode, data shifts into the shift register (Master Register) LSB from SER IN on the WR rising edge. In parallel mode, the Master Register loads with D3:0 (iff = 0000 through 1000), or the appropriate action is taken (iff = 1011 through 1111), on the WR rising edge (see Table 1). Synchronous Channel Switch Control Input. If EDGE/LEVEL = 1, data is loaded from the Master Register to the Slave Register on the rising edge of LATCH. If EDGE/LEVEL = 0, data is loaded from the Master to the Slave Register while LATCH 0. In parallel mode, commands 1011 through 1110 execute asynchronously, on the WR rising edge, regardless of the state of LATCH or EDGE/LEVEL. Parallel mode command 1111 executes a software "Latch" (see Table 1). Chip Enable. When = 0 and = 1, the WR line is enabled. Chip Enable. When = 0 and = 1, the WR line is enabled. Analog Video Outputs. Analog Ground. Parallel Data Bit Input D3 when SER/PAR D3 is unused with serial programming. Parallel Data Bit Input D2 when SER/PAR D2 is unused with serial programming. FUNCTION


 

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