Details, datasheet, quote on part number: HA457CN
CategoryCommunication => Network => Switches => Digital Crosspoint Switches
Description95MHz, Low Power, av = 2, 8 X 8 Video Crosspoint Switch
CompanyIntersil Corporation
DatasheetDownload HA457CN datasheet
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Features, Applications

The x 8 video crosspoint switch suitable for high performance video systems. Its high level of integration significantly reduces component count, board space, and cost. The crosspoint switch contains a digitally controlled matrix of 64 fully buffered switches that connect eight video input signals to any, or all, matrix outputs. Each matrix output connects to an internal, high-speed (275V/s), gain of two buffer capable of driving to 2.5V. The HA457 will directly drive a double terminated video cable with some degradation of differential gain and phase. Applications demanding the best composite video performance should drive the cable with a unity gain video buffer, such as the HFA1412 quad buffer (see Figure 7). This crosspoint's three-state output capability makes it feasible to parallel multiple HA457s and form larger switch matrices.


Pin Compatible, Cable Driving Upgrade for HA456 and MAX456 Fully Buffered Inputs and Outputs (AV = +2) Routes Any Input Channel to Any Output Channel Switches Standard and High Resolution Video Signals Serial or Parallel Digital Interface Expandable for Larger Switch Matrices Wide Bandwidth. 95MHz High Slew Rate. 275V/s Low Crosstalk 10MHz. -55dB

Video Switching and Routing Security and Video Editing Systems

PART NUMBER HA457CN HA457CM TEMP. RANGE (oC) to 70 PACKAGE 44 Ld MQFP 44 Ld PLCC PKG. NO. Q44.10x10 N44.65

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 321-724-7143 | Copyright Intersil Corporation 1999

PIN MQFP PLCC NAME NC D1/ SER OUT No connect. Not internally connected. Parallel Data Bit input D1 for parallel programming mode. Serial Data Output (MSB of shift register) for cascading multiple HA457s in serial programming mode. Simply connect Serial Data Out of one HA457 to Serial Data In of another HA457 to daisy chain multiple devices. Parallel Data Bit input D0 for parallel programming mode. Serial Data Input (input to shift register) for serial programming mode. Output Channel Address Bits. These inputs select the output being programmed in parallel programming mode. Analog Video Input Lines. FUNCTION

Digital Ground. Connect both DGND pins to AGND. A user strapped input that defines whether synchronous channel switching is edge or level controlled. With this pin strapped high, the slave register loads from the master register (thus changing the switch matrix state) on the rising edge of the LATCH signal. it is strapped low (level mode), the slave register is transparent while LATCH is low, passing data directly from the master register to the switch state decoders. Strapping EDGE/LEVEL and LATCH low causes the channel switch to execute on the WR rising edge (not recommended for serial mode operation). Positive supply voltage. Connect all V+ pins together and decouple each pin to AGND (Figure 6). A user strapped input that defines whether the serial (SER/PAR=1) or parallel (SER/PAR=0) digital programming interface is being utilized. Negative supply voltage. Connect both V- pins together and decouple each pin to AGND (Figure 6). WRITE Input. In serial mode, data shifts into the shift register (Master Register) LSB from SER IN on the WR rising edge. In parallel mode, the Master Register loads with D3:0 (iff D3:0=0000 through 1000), or the appropriate action is taken (iff D3:0=1011 through 1111), on the WR rising edge (see Table 1). Synchronous channel switch control input. If EDGE/LEVEL = 1, data is loaded from the Master Register to the Slave Register on the rising edge of LATCH. If EDGE/LEVEL = 0, data is loaded from the Master to the Slave Register while LATCH 0. In parallel mode, commands 1011 through 1110 execute asynchronously, on the WR rising edge, regardless of the state of LATCH or EDGE/LEVEL. Parallel mode command 1111 executes a software "Latch" (see Table 1). Chip Enable. When = 0 and = 1, the WR line is enabled. Chip Enable. When = 0 and = 1, the WR line is enabled. Analog Video Outputs.

Analog Ground. Parallel Data Bit Input D3 when SER/PAR D3 is unused with serial programming. Parallel Data Bit Input D2 when SER/PAR D2 is unused with serial programming.


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