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Details, datasheet, quote on part number:HCTS373DMSR
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Datasheet text preview:
TM
HCTS373MS
Radiation Hardened Octal Transparent Latch, Three-State
Pinouts
20 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP) MIL-STD-1835 CDIP2-T20 TOP VIEW
OE Q0 D0 D1 Q1 Q2 D2 D3 Q3 1 2 3 4 5 6 7 8 9 20 VCC 19 Q7 18 D7 17 D6 16 Q6 15 Q5 14 D5 13 D4 12 Q4 11 LE
August 1995
Features
· 3 Micron Radiation Hardened CMOS SOS · Total Dose 200K RAD (Si) · SEP Effective LET No Upsets: >100 MEV-cm2/mg · Single Event Upset (SEU) Immunity 1 x 1012 RAD (Si)/s · Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse · Latch-Up Free Under Any Conditions · Fanout (Over Temperature Range) - Bus Driver Outputs - 15 LSTTL Loads · Military Temperature Range: -55oC to +125oC · Significant Power Reduction Compared to LSTTL ICs · DC Operating Voltage Range: 4.5V to 5.5V · LSTTL Input Compatibility - VIL = 0.8V Max - VIH = VCC/2 Min · Input Current Levels Ii 5µA at VOL, VOH
GND 10
Description
The Intersil HCTS373MS is a Radiation Hardened octal transparent three-state latch with an active-low output enable. The outputs are transparent to the inputs when the Latch Enable (LE) is HIGH. When the Latch Enable (LE) goes LOW, the data is latched. The Output Enable (OE) controls the three-state outputs. When the Output Enable (OE) is HIGH, the outputs are in the high impedance state. The latch operation is independent of the state of the Output Enable. The HCTS373MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family. The HCTS373MS is supplied in a 20 lead Ceramic flatpack (K suffix) or a SBDIP Package (D suffix).
OE Q0 D0 D1 Q1 Q2 D2 D3 Q3 GND
20 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE (FLATPACK) MIL-STD-1835 CDFP4-F20 TOP VIEW
1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC Q7 D7 D6 Q6 Q5 D5 D4 Q4 LE
Ordering Information
PART NUMBER HCTS373DMSR HCT S373K MS R HCTS373D/Sample HCTS373K/Sample HCTS373HMSR TEMPERATURE RANGE -55oC to +125oC -55oC to +125oC + 2 5o C + 2 5o C + 2 5o C SCREENING LEVEL Intersil Class S Equivalent Intersil Class S Equivalent Sample Sample Die PACKAGE 20 Lead SBDIP 20 Lead Ceramic Flatpack 20 Lead SBDIP 20 Lead Ceramic Flatpack Die DB NA
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved 1
Spec Number File Number
518636 2131.2
HCTS373MS Functional Diagram
1 OF 8 (3, 4, 7, 8, 13, 14, 17, 18) D COMMON CONTROLS LE (11) LATCH OE D LE Q Q (2, 5, 6, 9, 12, 15, 16, 19)
OE (1)
TRUTH TABLE OE L L L L H H = High Level, X = Immaterial, LE H H L L X L = Low Level Z = High Impedance D H L I h X Q H L L H Z
I = Low voltage level prior to the high-to-low latch enable transition h = High voltage level prior to the high-to-low latch enable transition
Spec Number 2
518636
Specifications HCTS373MS
Absolute Maximum Ratings
Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VCC +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . . ±10mA DC Drain Current, Any One Output. . . . . . . . . . . . . . . . . . . . . . . ±25mA (All Voltage Reference to the VSS Terminal) Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (Soldering 10sec) . . . . . . . . . . . . . . . . . . +265oC Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Reliability Information
Thermal Resistance JA JC SBDIP Package. . . . . . . . . . . . . . . . . . . . 72oC/W 24oC/W Ceramic Flatpack Package . . . . . . . . . . . 107oC/W 28oC/W Maximum Package Power Dissipation at +125oC Ambient SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.69W Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 0.47W If device power exceeds package dissipation capability, provide heat sinking or derate linearly at the following rate: SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.9mW/oC Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . 9.3mW/oC
CAUTION: As with all semiconductors, stress listed under "Absolute Maximum Ratings" may be applied to devices (one at a time) without resulting in permanent damage. This is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The conditions listed under "Electrical Performance Characteristics" are the only conditions recommended for satisfactory device operation..
Operating Conditions
Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Input Rise and Fall Times at VCC = 4.5V (TR, TF) . . . . . 500ns Max Operating Temperature Range (TA) . . . . . . . . . . . . -55oC to +125oC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUP S 1 2, 3 Output Current (Sink) IOL VCC = 4.5V, VIH = 4.5V, VOUT = 0.4V, VIL = 0V 1 2, 3 Output Current (Source) IOH VCC = 4.5V, VIH = 4.5V, VOUT = VCC - 0.4V, VIL = 0V VCC = 4.5V, VIH = 2.25V, IOL = 50µA, VIL = 0.8V VCC = 5.5V, VIH = 2.75V, IOL = 50µA, VIL = 0.8V Output Voltage High VOH VCC = 4.5V, VIH = 2.25V, IOH = -50µA, VIL = 0.8V VCC = 5.5V, VIH = 2.75V, IOH = -50µA, VIL = 0.8V Input Leakage Current IIN VCC = 5.5V, VIN = VCC or GND 1 2, 3 1, 2, 3 LIMITS TEMPERATURE +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC, +125oC, -55oC MI N 7.2 6.0 -7.2 -6.0 MA X 40 750 0.1 UNITS µA µA mA mA mA mA V Input Low Voltage (VIL). . . . . . . . . . . . . . . . . . . . . . . . . 0.0V to 0.8V Input High Voltage (VIH) . . . . . . . . . . . . . . . . . . . . . . .VCC/2 to VCC
PARAMETER Quiescent Current
SYMBOL I CC
(NOTE 1) CONDITIONS VCC = 5.5V, VIN = VCC or GND
Output Voltage Low
VOL
1, 2, 3
+25oC, +125oC, -55oC
-
0.1
V
1, 2, 3
+25oC, +125oC, -55oC
VCC -0.1 VCC -0.1 -
-
V
1, 2, 3
+25oC, +125oC, -55oC
-
V
1 2, 3
+25oC +125oC, -55oC +25oC +125oC, -55oC +25oC, +125oC, -55oC
±0.5 ±5.0 ±1.0 ±50
µA µA µA µA -
Output Tri State Leakage
IOZ
VCC = 5.5V, VO = 0V or VCC
1 2, 3
Noise Immunity Functional Test NOTES:
FN
VCC = 4.5V, VIH = 2.25V, VIL = 0.8V (Note 2)
7, 8A, 8B
-
-
1. All voltages reference to device GND. 2. For functional tests VO 4.0V is recognized as a logic "1", and VO 0.5V is recognized as a logic "0".
Spec Number 3
518636
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