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Details, datasheet, quote on part number:HD-15530
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Datasheet text preview:
TM
HD-15530
CMOS Manchester Encoder-Decoder
Description
The Intersil HD-15530 is a high performance CMOS device intended to service the requirements of MlL-STD-1553 and similar Manchester II encoded, time division multiplexed serial data protocols. This LSI chip is divided into two sections, an Encoder and a Decoder. These sections operate completely independent of each other, except for the Master Reset functions. This circuit meets many of the requirements of MIL-STD1553. The Encoder produces the sync pulse and the parity bit as well as the encoding of the data bits. The Decoder recognizes the sync pulse and identifies it as well as decoding the data bits and checking parity. This integrated circuit is fully guaranteed to support the 1MHz data rate of MlL-STD-1553 over both temperature and voltage. It interfaces with CMOS, TTL or N channel support circuitry, and uses a standard 5V supply. The HD-15530 can also be used in many party line digital data communications applications, such as an environmental control system driven from a single twisted pair cable of fiber optic cable throughout the building.
March 1997
Features
· Support of MlL-STD-1553 · Data Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.25 MBit/s · Sync Identification and Lock-In · Clock Recovery · Manchester II Encode, Decode · Separate Encode and Decode · Low Operating Power . . . . . . . . . . . . . . . . . 50mW at 5V
Ordering Information
P ACKAGE CE RDIP SMD# CL CC SMD# PD IP -40oC to +85oC -40oC to +85oC -55oC to +125oC TE MP . RANGE -40oC to +85oC -55oC to +125oC 1.25 MEGABIT/s HD1-15530-9 HD1-15530-8 7802901JA HD4-15530-9 HD4-15530-8 78029013A HD3-15530-9 E24.6 J28.A PKG. NO. F24.6
Pinouts
HD-15530 (CERDIP, PDIP) TOP VIEW
SERIAL DATA OUT VA LID WORD 1 ENCODER SHIFT CLK 2 TAKE DATA 3 SERIAL DATA OUT 4 DECODER CLK 5 24 VCC 23 ENCODER CLK 22 SEND CLK IN 21 SEND DATA 20 SYNC SELECT 19 ENCODER ENABLE 18 SERIAL DATA IN 17 BIPOLA R ONE OUT 16 OUTPUT INHIBIT BIPOLA R 15 ZERO OUT 14 ÷ 6 OUT 13 MASTER RESET DECODER CLK NC NC BIPOLAR ZERO IN BIPOLAR ONE IN UNIPOLAR DATA IN DECODER SHIFT CLK 5 6 7 8 9 10 11 12 COMMAND/ DATA SYNC 13 DECODER RESET 14 GND 15 MA STER RESET 16 17 BIPOLAR ZER O OUT 18 OUTPUT INHIBIT
HD-15530 (CLCC) TOP VIEW
TAKE DATA ENCODER SHIFT CLK ENCODER CL K SEN D CLK IN 27 26 25 24 23 22 21 20 19
VALID WORD 1
4
3
2
V CC 28
SEND DAT A NC NC SYNC SELECT ENCODER ENABLE SERIAL DATA IN BIPOLAR ONE OUT
BIPOLAR ZERO IN 6 BIPOLAR ONE IN 7
U NIPOLA R DATA IN 8 DECODER SHIFT CLK 9 COMMAND/ DATA SYNC 10 DECODER RESET 11 GND 12
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved
÷ 6 OUT
FN2960.1
142
HD-15530 Block Diagrams
E NCODER
12 13 22 14 G ND MASTER RESET SEND CLK IN VCC OUTPUT INHIBIT 24 UNIPOLAR 8 DATA IN BIPOLAR 7 ONE IN BIPOLAR 6 ZERO IN
DECODER
3 TRANSI TION FINDER CHARACTER IDENTIFIER T AKE DAT A
÷ 6 OUT ÷6
ENCODER CL K BIT COUNTER
÷2
17 CHARAC TER FORMER 15
16 BIPOLAR ONE OUT BIPOLAR ZERO OUT
10 COMMAND/ DA TA SYNC 4 SERIAL DATA OUT
23
DECODER CL K 18 19 20 SYNC SELECT MASTER RESET
5
SYNCHRONIZER
BIT RAT E CL K
PARITY 1 VALID CHECK WORD 9 DECODER SHIFT CL K
21
2
13 DECODER RESET 11 BIT COUNTER
SEND D ATA
SERIAL DATA IN
ENCOD ER E NABL E ENCODER SHIFT CLK
Pin Description
PIN NUMBER 1 2 3 4 5 TYPE O O O O I NAM E V ALID WORD E NCODER SHIFT CLOCK TAKE DATA S ERIAL DATA OUT DE CODER CLOCK SECTION Decoder Encoder Decoder Decoder Decoder D ESCRIPTION Output high indicates receipt of a valid word, (valid parity and no Manchester errors). Output for shifting data into the Encoder. The Encoder samples SDI on the low- to-high transition of Encoder Shift Clock. Output is high during receipt of data after identification of a sync pulse and two valid Manchester data bits. D elivers received data in correct NRZ format. Input drives the transition finder, and the synchronizer which in turn supplies the clock to the balance of the decoder, input a frequency equal to 12X the data rate. A high input should be applied when the bus is in its negative state. This pin must be held high when the Unipolar input is used. A high input should be applied when the bus is in its positive state. This pin must be held low when the Unipolar input is used. With pin 6 high and pin 7 low, this pin enters unipolar data into the transition finder circuit. If not used this input must be held low. Output which delivers a frequency (DECODER CLOCK ÷ 12), synchronized by the recovered serial data stream. Output of a high from this pin occurs during output of decoded data which w as preceded by a Command (or Status) synchronizing character. A low output indicates a Data synchronizing character. A high input to this pin during a rising edge of DECODER SHIFT CLOCK r esets the decoder bit counting logic to a condition ready for a new word. Ground Supply pin. A high on this pin clears 2:1 counters in both Encoder and Decoder, and r esets the ÷ 6 circuit. Output from 6:1 divider which is driven by the ENCODER CLOCK. An active low output designed to drive the zero or negative sense of a bipolar line driver. A low on this pin forces pin 15 and 17 high, the inactive states. An active low output designed to drive the one or positive sense of a bipolar line driver.
6 7 8 9 10
I I I O O
BIPOLAR ZERO IN B IPOLAR ONE IN UN LPOLAR DATA IN DECODER SHIFT CLOCK COMMAND SYNC
Decoder Decoder Decoder Decoder Decoder
11 12 13 14 15 16 17
I I I O O I O
DE CODER RESET G RO UND MAS TER RESET
Decoder Both Both Encoder Encoder Encoder Encoder
÷ 6 OUT
B IPOLAR ZERO OUT OUTPUT INHIBIT B IPOLAR ONE OUT
143
HD-15530 Pin Description
PIN NUMBER 18 19 20 21 22 23 24 I = Input TYPE I I I O I I I (Continued)
NAM E S ERIAL DATA IN ENCODER ENABLE S YNC SELECT S END DATA SEND CLOCK IN E NCODER CLOCK VCC
SECTION Encoder Encoder Encoder Encoder Encoder Encoder Both
D ESCRIPTION Accepts a serial data stream at a data rate equal to ENCODER SHIFT C LOCK. A high on this pin initiates the encode cycle. (Subject to the preceeding cycle being complete.) Actuates a Command sync for an input high and Data sync for an input low. An active high output which enables the external source of serial data. C lock input at a frequency equal to the data rate X2, usually driven by ÷ 6 output. Input to the 6:1 divider, a frequency equal to the data rate X12 is usually input here. VCC is the +5V power supply pin. A 0.1µF decoupling capacitor from VCC ( pin 24) to GROUND (pin 12) is recommended.
O = Output
Encoder Operation
The Encoder requires a single clock with a frequency of twice the desired data rate applied at the SEND CLOCK input. An auxiliary divide by six counter is provided on chip which can be utilized to produce the SEND CLOCK by dividing the DECODER CLOCK. The Encoder's cycle begins when ENCODER ENABLE is high during a falling edge of ENCODER SHIFT CLOCK 1 . This cycle lasts for one word length or twenty ENCODER SHIFT CLOCK periods. At the next low-to-high transition of the ENCODER SHIFT CLOCK, a high SYNC SELECT input actuates a command sync or a low will produce a data sync for the word 2 . When the Encoder is ready to accept data, the SEND DATA output will go high and remain high for sixteen ENCODER SHIFT CLOCK periods 3 . During these sixteen periods the data should be clocked into the SERIAL DATA input with every high-to-low transition of the ENCODER SHIFT CLOCK so it can be sampled on the lowto-high transition 3 - 4 . After the sync and Manchester II coded data are transmitted through the BIPOLAR ONE and BIPOLAR ZERO outputs, the Encoder adds on an additional bit which is the parity for that word 5 . If ENCODER ENABLE is held high continuously, consecutive words will be encoded without an interframe gap. ENCODER ENABLE must go low by time 5 as shown to prevent a consecutive word from being encoded. At any time a low on OUTPUT INHIBIT input will force both bipolar outputs to a high state but will not affect the Encoder in any other way. To abort the Encoder transmission a positive pulse must be applied at MASTER RESET. Anytime after or during this pulse, a low-to-high transition on SEND CLOCK clears the internal counters and initializes the Encoder for a new word.
TIMIN G SEND CLK ENCODER SHI FT CLK ENCODER E NABL E SYNC SELECT SEND DATA SERIAL DA TA IN BIPOLAR ONE OUT BIPOLAR ZERO OUT 12
0
1
2
3
4
5
6
7
15
16
17
18
19
DON'T CARE VALID DON'T CARE
15
1ST HALF 2ND HALF
14 15 15 14 14
13 13 13
12 12 12
11 11 11
10
3 3 3
2 2 2
1 1 1
0 0 0 4 5 P P
SYNC
SYNC 3
FIGURE 1.
144
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