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Details, datasheet, quote on part number:HD-15531
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Datasheet text preview:
TM
HD-15531
CMOS Manchester Encoder-Decoder
Description
The Intersil HD-15531 is a high performance CMOS device intended to service the requirements of MIL-STD-1553 and similar Manchester II encoded, time division multiplexed serial data protocols. This LSI chip is divided into two sections, an Encoder and a Decoder. These sections operate independently of each other, except for the master reset and word length functions. This circuit provides many of the requirem ents of MIL-STD-1553. The Encoder produces the sync pulse and the parity bit as well as the encoding of the data bits. The Decoder recognizes the sync pulse and identifies it as well as decoding the data bits and checking parity. The HD-15531 also surpasses the requirements of MILSTD-1553 by allowing the word length to be programmable (from 2 to 28 data bits). A frame consists of three bits for sync followed by the data word (2 to 28 data bits) followed by one bit of parity, thus, the frame length will vary from 6 to 32 bit periods. This chip also allows selection of either even or odd parity for the Encoder and Decoder separately. This integrated circuit is fully guaranteed to support the 1MHz data rate of MIL-STD-1553 over both temperature and voltage. For high speed applications the 15531B will support a 2.5 Megabit/sec data rate. The HD-15531 can also be used in many party line digital data communications applications, such as a local area network or an environmental control system driven from a single twisted pair of fiber optic cable throughout a building.
March 1997
Features
· Support of MIL-STD-1553 · Data Rate (15531B) . . . . . . . . . . . . . . . .2.5 Megabit/Sec · Data Rate (15531) . . . . . . . . . . . . . . . . .1.25 Megabit/Sec · Variable Frame Length to 32 Bits · Sync Identification and Lock-In · Separate Manchester II Encode, Decode · Low Operating Power . . . . . . . . . . . . . . . . . 50mW at 5V
Ordering Information
PACKAGE
PDIP CERDIP
TEMP. RANGE (oC) -40 to 85 -40 to 85 -55 to 125
1.25MBIT /SEC HD1-15531-9 HD1-15531-8 59629054901MQA 59629054902MQA
2.5MBIT /SEC
PKG. NO.
HD3-15531B-9 E 40.6 HD1-15531B-9 F40.6 HD1-15531B-8 F40.6 HD1-15531
DESC (CERDIP)
-55 to 125 -55 to 125
F40.6 F40.6
HD1-15531B
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved
FN2961.1
1
HD-15531 Pinout
HD-15531 (CERDIP, PDIP) TOP VIEW
V CC VALID WORD TAKE DATA' TAKE DATA SERIAL DATA OUT SYNCHR DATA SYNCHR DATA SEL SYNCHR CLK DECODER CLK 1 2 3 4 5 6 7 8 9 40 COUNT C1 39 COUNT C4 38 DATA SYNC 37 ENCODER CLK 36 COUNT C3 35 NC 34 ENCODER SHIFT CLK 33 SEND CLK IN 32 SEND DATA 31 ENCODER PARITY SEL 30 SYNC SEL 29 ENCODER ENABLE 28 SERIAL DATA IN 27 BIPOLAR ONE OUT 26 OUTPUT INHIBIT 25 24 BIPOLAR ZERO OUT
SYNCHR CLK SEL 10 BIPOLAR ZERO IN 11 BIPOLAR ONE IN 12 UNIPOLAR DATA IN 13 DECODER SHIFT CLK 14 TRANSITION SEL 15 NC 16 COMMAND SYNC 17 DECODER PARITY SEL 18 DECODER RESET 19 COUNT C0 20
÷ 6 OUT
23 COUNT C2 22 MASTER RESET 21 GND
Block Diagrams
ENDODER
G ND MASTER RESET SEND CLK IN VCC OUTPUT INHIBIT
21 22 33 24
1
÷ 6 OUT ÷2 ÷6
ENCODER CL K BIT COUNTER 20 C0 40 C1 23 C2 36 C3 39 C4 32 34 28 29 30 31 SEND DAT A SERIAL DATA IN SYNC SELECT ENCODER PARITY SELECT 27 CHARACTER FORMER
26
BI POLAR ONE OUT BI POLAR ZERO OUT
25
37
ENCODER SHIFT CL K
ENCODER ENA BLE
2
HD-15531
DECODER
SYNCHRONOUS DATA SELECT UNIPOLAR DATA IN BIPOLAR ONE IN BIPOLAR ONE IN 13 12 11 TRANSITI ON FINDER DAT A SELECT GATE C HARACTER IDENTIFI ER 7 8 SYNCHRONOUS DAT A 4 17 TAKE DATA COMMAND SYNC DATA SYNC 5 DECODER CL K DECODER CLK SELECT SYNCH RONOUS CL K SYNCH RONOUS CLK SELECT MASTER RESET 9 15 SYNCHRONIZER 8 10 22 19 20 40 C0 3 39 C3 C4 CLOCK SELECT DAT A BIT RAT E CL K 2 PARI TY CHE CK 1 6 SERIAL DATA OUT VALID WORD P ARIT Y SELECT DECODER SHIFT CLK
14
DECODER RESET
B IT COUNTER 23 C1 C2 36
TAKE DATA'
Pin Description
PIN NU MBE R 1 2 3 O O TYPE VCC VALID WORD TA KE DATA' NAM E SECTION Both Decoder Decoder DESC RIPTION Positive supply pin. A 0.1µF decoupling capacitor from VCC (pin 1) to GROUND (pin 21) is recommended. Output high indicates receipt of a valid word, (valid parity and no Manchester errors) . A continuous, free running signal provided for host timing or data handling. When data is present on the bus, this signal will be synchronized to the incoming data and will be identical to TAKE DATA. Output is high during receipt of data after identification of a valid sync pulse and two valid Manchester bits. D elivers received data in correct NRZ format. Input presents Manchester data directly to character identification logic. SYNCHRONOUS DATA SELECT must be held high to use this input. If not used, this pin must be held high. In high state allows the synchronous data to enter the character identification logic. Tie this input low for asynchronous data. Input provides externally synchronized clock to the decoder, for use when receiving synchronous data. This input must be tied high when not in use. Input drives the transition finder, and the synchronizer which in turn supplies the clock to the balance of the decoder. Input a frequency equal to 12X the data rate. In high state directs the SYNCHRONOUS CLOCK to control the decoder character identification logic. A low state selects the DECODER CLOCK. A high input should be applied when the bus is in its negative state. This pin must be held high when the unipolar input is used. A high input should be applied when the bus is in its positive state. This pin must he held low when the unipolar input is used. With pin 11 high and pin 12 low, this pin enters unipolar data into the transition finder circuit. If not used this input must be held low.
4 5 6
O O I
TA KE DATA SERIAL DATA OUT SYNCH RONOU S DATA SYNCH RONOU S DATA SELECT SYNCH RONOU S CLOCK DECODER CLOCK SYNCH RONOU S CLOCK SELCT BIP OLAR ZERO IN BIP OLAR ONE IN UNIP OLAR DATA IN
Decoder Decoder Decoder
7 8 9 10 11 12 13
I I I I I I I
Decoder Decoder Decoder Decoder Decoder Decoder Decoder
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