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Details, datasheet, quote on part number:HD-15531/883
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Datasheet text preview:
TM
HD-15531/883
CMOS Manchester Encoder-Decoder
Description
The Intersil HD-15531/883 is a high performance CMOS device intended to service the requirements of MIL-STD1553 and similar Manchester II encoded, time division multiplexed serial data protocols. This LSI chip is divided into two sections, an Encoder and a Decoder. These sections operate independently of each other, except for the master reset and word length functions. This circuit provides many of the requirem ents of MIL-STD-1553. The Encoder produces the sync pulse and the parity bit as well as the encoding of the data bits. The Decoder recognizes the sync pulse and identifies it as well as decoding the data bits and checking parity. The HD-15531/883 also surpasses the requirements of MILSTD-1553 by allowing the word length to be programmable (from 2 to 28 data bits). A frame consists of three bits for sync followed by the data word (2 to 28 data bits) followed by one bit of parity, thus, the frame length will vary from 6 to 32 bit periods. This chip also allows selection of either even or odd parity for the Encoder and Decoder separately. This integrated circuit is fully guaranteed to support the 1MHz data rate of MIL-STD-1553 over both temperature and voltage. For high speed applications the 15531B will support a 2.5 Megabit/sec data rate. The HD-15531/883 can also be used in many party line digital data communications applications, such as a local area network or an environmental control system driven from a single twisted pair or fiber optic cable throughout a building.
March 1997
Features
· This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. · Support of MIL-STD-1553 · Data Rate (15531B) . . . . . . . . . . . . . . . .2.5 Megabit/Sec · Data Rate (15531) . . . . . . . . . . . . . . . . .1.25 Megabit/Sec · Variable Frame Length to 32-Bits · Sync Identification and Lock-In · Separate Manchester II Encode, Decode · Low Operating Power . . . . . . . . . . . . . . . . . 50mW at 5V
Ordering Information
P ACKAGE CERDIP TEMPERATU RE RANGE -55oC to +125oC 1.25MBIT/SEC HD1-15531/883 2.5MBIT/SEC HD1-15531B/883 PKG. NO. F40.6
FN2962.1
170
HD-15531/883 Pinout
HD-15531/883 (CERDIP) TOP VIEW
VCC VALID WORD TAKE DATA' TAKE DATA SERIAL DATA OUT SYNCHR DATA SYNCHR DATA SEL SYNCHR CLK DECODER CLK 1 2 3 4 5 6 7 8 9 40 COUNT C1 39 COUNT C4 38 DATA SYNC 37 ENCODER CLK 36 COUNT C3 35 NC 34 ENCODER SHIFT CLK 33 SEND CLK IN 32 31 30 29 SEND DATA ENCODER PARITY SEL SYNC SEL ENCODER ENABLE
SYNCHR CLK SEL 10 BIPOLAR ZERO IN 11 BIPOLAR ONE IN 12 UNIPOLAR DATA IN 13 DECODER SHIFT CLK 14 TRANSITION SEL 15 NC 16 COMMAND SYNC 17 DECODER PARITY SEL 18 DECODER RESET 19 COUNT C0 20
28 SERIAL DATA IN 27 BIPOLAR ONE OUT 26 OUTPUT INHIBIT 25 24 BIPOLAR ZERO OUT
÷ 6 OUT
23 COUNT 2 22 MASTER RESET 21 GND
Block Diagrams
ENCODER
G ND MASTER RESET SEND CLK IN 6 OUT VCC OUTPUT INHIBIT
21 22 33 24
1
26
÷2 ÷6
ENCODER CL K BIT COUNTER 20 C0 40 C1 23 C2 36 C3 39 C4 32 34 28
27 CHARACTER FORMER
BI POLAR ONE OUT BI POLAR ZERO OUT
25
37
29
30
31
SEND DAT A
SERIAL DATA IN
SYNC SELECT ENCODER PARITY SELECT
ENCODER SHIFT CL K
ENCODER ENA BLE
171
HD-15531/883 Block Diagrams
(Continued) DECODER
SYNCHRONOUS DATA SELECT UNIPOLAR DATA IN BIPOLAR ONE IN BIPOLAR ZERO IN 13 12 11 TRANSITI ON FINDER DAT A SELECT GATE C HARACTER IDENTIFI ER 7 8 SYNCHRONOUS DAT A 4 17 38 5 DECODER CL K DECODER CLK SELECT SYNCH RONOUS CL K SYNCH RONOUS CLK SELECT MASTER RESET 9 15 SYNCHRONIZER 8 10 22 19 20 40 C0 3 39 C3 C4 CLOCK SELECT DAT A BIT RAT E CL K 2 PARI TY 16 CHE CK TAKE DATA COMMAND DATA SYNC SERIAL DATA OUT VALID WORD P ARIT Y SELECT DECODER SHIFT CLK
14
DECODER RESET
B IT COUNTER 23 36
TAKE DATA
C1 C2
172
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