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Details, datasheet, quote on part number:HD-4702/883
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Datasheet text preview:
TM
HD-4702/883
CMOS Programmable Bit Rate Generator
Description
The HD-4702/883 Bit Rate Generator provides the necessary clock signals for digital data transmission systems, such as a UART. It generates 13 commonly used bit rates using an on-chip crystal oscillator or an external input. For conventional operation generating 16 output clock pulses per bit period, the input clock frequency must be 2.4576M Hz (i.e., 9600 Baud x 16 x 16, since there is an internal ÷ 16 prescaler). A lower input frequency will result in a proportionally lower output frequency. The HD-4702/883 can provide multi-channel operation with a minimum of external logic by having the clock frequency CO and the ÷ 8 prescaler outputs Q0 , Q1 , Q2 available externally. All signals have a 50% duty cycle except 1800 Baud, which has less than 0.39% distortion. The four rate select inputs (S0-S3) select which bit rate is at the output (Z). See Truth Table for Rate Select Inputs for select code and output bit rate. Two of the 16 select codes for the HD-4702/883 do not select an internally generated frequency, but select an input into which the user can feed either a different frequency, or a static level (High or Low) to generate "ZERO BAUD". The bit rates most commonly used in modern data terminals (110,150, 300,1200, 2400 Baud) require that no more than one input be grounded for the HD-4702/883, which is easily achieved with a single 5-position switch. The HD-4702/883 has an initialization circuit which generates a master reset for the scan counter. This signal is derived from a digital differentiator that senses the first high level on the CP input after the EC P input goes low. When ECP is high, selecting the crystal input, CP must be low. A high level on CP would apply a continuous reset. See Clock Modes and Initialization below.
June 1998
Features
· This Circuit is Processed in Accordance to MIL-STD-883 and is Fully Conformant Under the Provisions of Paragraph 1. 2. 1. · HD-4702/883 Provides 13 Commonly Used Bit Rates · Uses a 2.4576MHz Crystal/Input for Standard Frequency Output (16 Times Bit Rate) · Low Power Dissipation · Conforms to ElA RS-404 · One HD-4702/883 Controls up to Eight Transmission Channels · Initialization Circuit Facilitates Diagnostic Fault Isolation · On-Chip Input Pull-Up Circuit
Ordering Information
PART NUMBER HD1-4702/883 TEMPERATU RE RANGE (oC) -55 to 125 PACKAGE CERDIP PKG. NO. F16.3
Pinout
HD-4702/883 (CERDIP) TOP VIEW
Q0 Q1 Q2 ECP CP OX IX GND 1 2 3 4 5 6 7 8 16 VCC 15 IM 14 S0 13 S1 12 S2 11 S3 10 Z 9 CO
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved
FN2955.2
1
HD-4702/883 Truth Table
TRUTH TABLE FOR RATE SELECT INPUTS (Using 2.4576MHz Crystal) S3 L L L L L L L L H H H H H H H H NOTE: 1. 19200 Baud by connecting Q2 to IM . S2 L L L L H H H H L L L L H H H H S1 L L H H L L H H L L H H L L H H S0 L H L H L H L H L H L H L H L H OUTPUT RATE (Z) MUX Input (lM) MUX Input (lM) 50 Baud 75 Baud 134.5 Baud 200 Baud 600 Baud 2400 Baud 9600 Baud 4800 Baud 1800 Baud 1200 Baud 2400 Baud 300 Baud 150 Baud 110 Baud X X X NOTE: 2. Actual output frequency is 16 times the indicated output rate, assuming a clock frequency of 2.4576MHz. H L X = HIGH Level = LOW Level = Don't Care = Clock Pulse = First HIGH Level Clock Pulse after ECP goes LOW IX CLOCK MODES AND INITIALIZATION ECP H L H L H CP L OPERATION Clocked from IX Clocked from CP Continuous Reset Reset During First CP = High Time
2
HD-4702/883
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V Input, Output or I/O Voltage . . . . . . . . . . . GND -0.5V to VCC +0.5V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Typical Derating Factor . . . . . . . . . . . 1mA/MHz Increase in ICCOP
Thermal Information
Thermal Resistance, (Typical, Note 3) CERD IP Package . . . . . . . . . . . . . .
JA (oC/W) JC (oC/W)
78 23
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range. . . . . . . . . . . . . . . . . -55oC to 125oC
Maximum Storage Temperature Range . . . . . . . . . . - 65oC to 150oC Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 175oC Maximum Lead Temperature (Soldering, 10s) . . . . . . . . . . . . 300oC
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720 Gates
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 3. JA is measured with the component mounted on an evaluation PC board in free air. TABLE 1. D C ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested GROUP A SUBGROUPS 1, 2, 3 1, 2, 3 1, 2, 3 TEMPERATURE ( oC) -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125
DC PARAMETER Input High Voltage Input Low Voltage Output High Voltage
SY MBOL VIH VIL VOH1 VOL1 IIH IILX I lL IOHX
CONDITIONS VCC = 4.5V VCC = 4.5V IOH -1µA, VCC = 4.5V, (Note 4) IOL +1µA, VCC = 4 5V, (Note 4) VIN = VCC . All Other Pins = 0V, VCC = 5.5V VIN = 0V, All Other Pins = VCC , VCC = 5.5V VIN = 0V All Other Pins = VCC , VCC = 5.5V (Note 5) VOUT = VCC -0.5, VCC = 4.5V Input at 0V or VCC per Logic Function or Truth Table VOUT = 2.5V, VCC = 4.5V Input at 0V or VCC per Logic Function or Truth Table VOUT = VCC -0.5, VCC = 4.5V Input at 0V or VCC per Logic Function or Truth Table VOUT = 0.4V, VCC = 4.5V Input at 0V or VCC per Logic Function or Truth Table VOUT = 0.4V, VCC = 4.5V Input at 0V or VCC per Logic Function or Truth Table
MIN VCC 70% V CC -0.1 -
M AX VCC 30% -
UNITS V V V
Output Low Voltage
1, 2, 3
0.1
V µA µA µA mA
Input High Current
1, 2, 3
-1
+1
Input Low Current ( IX Input) Input Low Current ( All Other Inputs) Output High Current ( OX )
1, 2, 3
-1
+1
1, 2, 3 1, 2, 3
-0.1
-100 -
Output High Current (All Other Outputs) Output High Current (All Other Outputs)
IOH1
1, 2, 3
-55 TA 125
-1.0
-
mA
IOH2
1, 2, 3
-55 TA 125
-0.3
-
mA
Output Low Current (OX) Output Low Current (All Other Outputs)
IOLX
1, 2, 3
-55 TA 125
0.1
-
mA
IOL
1, 2, 3
-55 TA 125
1.6
-
mA
3
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