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Details, datasheet, quote on part number:HD-6402
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Datasheet text preview:
TM
HD-6402
CMOS Universal Asynchronous Receiver Transmitter (UART)
Description
The HD-6402 is a CMOS UART for interfacing computers or microprocessors to an asynchronous serial data channel. The receiver converts serial start, data, parity and stop bits. The transmitter converts parallel data into serial form and automatically adds start, parity and stop bits. The data word length can be 5, 6, 7 or 8 bits. Parity may be odd or even. Parity checking and generation can be inhibited. The stop bits may be one or two or one and one-half when transmitting 5-bit code. The HD-6402 can be used in a wide range of applications including modems, printers, peripherals and remote data acquisition systems. Utilizing the Intersil advanced scaled SAJI IV CMOS process permits operation clock frequencies up to 8.0MHz (500K Baud). Power requirements, by comparison, are reduced from 300mW to 10mW. Status logic increases flexibility and simplifies the user interface.
March 1997
Features
· 8.0M Hz Operating Frequency (HD-6402B) · 2.0M Hz Operating Frequency (HD-6402R) · Low Power CMOS Design · Programmable Word Length, Stop Bits and Parity · Automatic Data Formatting and Status Generation · Compatible with Industry Standard UARTs · Single +5V Power Supply · CMO S/TTL Compatible Inputs
Ordering Information
PACKAGE Plastic DIP CERDIP SMD# TEMPERATU RE RANGE -40oC to +85oC -40oC to +85oC -55oC to +125oC 2MHz = 125K BAUD HD 3-6402R-9 HD 1-6402R-9 5962-9052501MQA 8MHz = 500K BAUD HD 3-6402B- 9 HD 1-6402B- 9 5962-9052502MQA PKG. NO. E40.6 F40.6 F40.6
Pinout
HD- 6402 (PDIP, CERDIP) TOP VIEW
VCC NC G ND RRD RBR8 RBR7 RBR6 RBR5 RBR4 RBR3 RBR2 RBR1 PE FE OE S FD RRC DRR DR R RI
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 TRC 39 EPE 38 CLS1 37 CLS2 36 SBS 35 PI 34 CRL 33 TBR8 32 TBR7 31 TBR6 30 TBR5 29 TBR4 28 TBR3 27 TBR2 26 TBR1 25 TRO 24 TRE 23 TBRL 22 TBRE 21 MR
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2001. All Rights Reserved
File Number
2956.1
1
HD-6402 Functional Diagram
T BR8 (24) TRE (22) TBRE (23) TBRL (40) TRC TRANSMITTER TIMING AND CONTROL STOP PARITY LOGIC (33 ) (32) (31) (30 ) (29) (28) (2 7) (26) TBR1
TRANSMITTER BUFFER REGISTER TRANSMITTER REGISTER MULTIPLEXER (25 ) TRO START
(38 ) CLS1 (37 ) CLS2 (34) CRL (2 1) MR
CONTROL REGISTER
(36 ) SBS (16 ) SFD (39 ) EPE (35 ) PI (20 ) RRI
(17) RRC (18) DRR (19) DR
RECEIVER TIMING AND CONTROL STOP LOGIC P ARIT Y LOGIC
MULTIPLEXER RECEIVER REGISTER RECEI VER BUFFER REGISTER
START LOGIC
(16) SFD THESE OUTPUTS ARE THREE-STATE
3-STATE BUFFERS RBR8 OE (15) FE (14) PE (13) RBR1 (5 ) (6 ) (7 ) (8 ) (9) (1 0) (1 1) (12)
(4) RRD
Control Definition
CONTROL WORD CLS 2 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 CLS 1 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 PI 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 0 1 1 EPE 0 0 1 1 X X 0 0 1 1 X x 0 0 1 1 X x 0 0 1 1 X x SBS 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 START BIT 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CHA RACTER FORMAT DATA BITS 5 5 5 5 5 5 6 6 6 6 6 6 7 7 7 7 7 7 8 8 8 8 8 8 PARITY BIT O DD O DD EVEN EVEN NO NE NO NE O DD O DD EVEN EVEN NO NE NO NE O DD O DD EVEN EVEN NO NE NO NE O DD O DD EVEN EVEN NO NE NO NE STOP BITS 1 1.5 1 1.5 1 1.5 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
2
HD-6402 Pin Description
PIN T YPE SYMBOL 1 2 3 4 I VCC NC GND RRD No Connection Ground A high level on RECEIVER REGISTER DISABLE forces the receiver holding out-puts RBR1-RBR8 to high impedance state. The contents of the RECEIVER BUFFER REGISTER appear on these three-state outputs. Word formats less than 8 characters are right justified to RBR1. See Pin 5-RBR8 See Pin 5-RBR8 See Pin 5-RBR8 See Pin 5-RBR8 See Pin 5-RBR8 See Pin 5-RBR8 See Pin 5-RBR8 A high level on PARITY ERROR indicates received parity does not match parity programmed by control bits. When parity is inhibited this output is low. A high level on FRAMING ERROR indicates the first stop bit was invalid. A high level on OVERRUN ERROR indicates the data received flag was not cleared before the last character was transferred to the receiver buffer register. A high level on STATUS FLAGS DISABLE forces the outputs PE, FE, OE, DR, TBRE to a high impedance state. T he Receiver register clock is 16X the receiver data rate. A low level on DATA RECEIVED RESET clears the data received output DR to a low level. A high level on DATA RECEIVED indicates a character has been received and transferred to the receiver buffer register. Serial data on RECEIVER REGISTER INPUT is clocked into the receiver register. A high level on MASTER RESET clears PE, FE, OE and DR to a low level and sets the transmitter register empty (TRE) to a high level 18 clock cycles after MR falling edge. MR does not clear the receiver buffer register. This input must be pulsed at least once after power up. The HD-6402 must be master reset after power up. The reset pulse should meet VIH and tMR. Wait 18 clock cycles after the falling edge of MR before beginning operation. A high level on TRANSMITTER BUFFER REGISTER EMPTY indicates the transmitter buffer register has transferred its data to the transmitter register and is ready for new data. A low level on TRANSMITTER BUFFER REGIST ER LOAD transfers data from inputs TBR1T BR8 into the transmitter buffer register. A low to high transition on TBRL initiates data transfer to the transmitter register. If busy, transfer is automatically delayed so that the two characters are transmitted end to end. 40 I TR C 38 39 I I CLS1 EPE 35 36 I I PI SBS 25 26 O I TR O TR B 1 DESCRIPTION Positive Voltage Supply PIN TYPE SYMBOL 24 O TR E DESCRIPTION A high level on TRANSMITTER REGISTER EMPT Y indicates completed transmission of a character including stop bits. Character data, start data and stop bits appear serially at the TRANSMITTER REGISTER OUTPUT. Character data is loaded into the TRANSMITTER BUFFER REGISTER via inputs TBR1-TBR8. For character formats less than 8 bits the TBR8, 7 and 6 inputs are ignored corresponding to their programmed word length. See Pin 26-TBR1. See Pin 26-TBR1. See Pin 26-TBR1. See Pin 26-TBR1. See Pin 26-TBR1. See Pin 26-TBR1. See Pin 26-TBR1. A high level on CONTROL REGISTER LOAD loads the control register with the control word. The control word is latched on the falling edge of CRL. CRL may be tied high. A high level on PARITY INHIBIT inhibits parity generation, parity checking and forces PE output low. A high level on STOP BIT SELECT selects 1.5 stop bits for 5 character format and 2 stop bits for other lengths. T hese inputs program the CHARACTER LENGTH SELECTED (CLS1 low CLS2 low 5 bits) (CLS1 high CLS2 low 6 bits) (CLS1 low CLS2 high 7 bits) (CLS1 high CLS2 high 8 bits.) See Pin 37-CLS2. When PI is low, a high level on EVEN PARITY ENABLE generates and checks even parity. A low level selects odd parity. T he TRANSMITTER REGISTER CLOCK is 16X the transmit data rate.
5
O
RBR8
27 28 29 30 31 32 33 34
I I I I I I I I
TB R 2 TB R 3 TB R 4 TB R 5 TB R 6 TB R 7 TB R 8 CRL
6 7 8 9 10 11 12 13
O O O O O O O O
RBR7 RBR6 RBR5 RBR4 RBR3 RBR2 RBR1 PE
14 15
O O
FE OE
37
I
CLS2
16
I
S FD
17 18 19
I I O
RRC DRR DR
20 21
I I
RRI MR
A 0.1µF decoupling capacitor from the VCC pin to the GND is recommended.
22
O
TBRE
23
I
TB R L
3
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