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Details, datasheet, quote on part number:HD1-15531/883
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Datasheet text preview:
HD-15531/883
March 1997
CMOS Manchester Encoder-Decoder
Description
The Intersil HD-15531/883 is a high performance CMOS device intended to service the requirements of MIL-STD1553 and similar Manchester II encoded, time division multiplexed serial data protocols. This LSI chip is divided into two sections, an Encoder and a Decoder. These sections operate independently of each other, except for the master reset and word length functions. This circuit provides many of the requirements of MIL-STD-1553. The Encoder produces the sync pulse and the parity bit as well as the encoding of the data bits. The Decoder recognizes the sync pulse and identifies it as well as decoding the data bits and checking parity. The HD-15531/883 also surpasses the requirements of MILSTD-1553 by allowing the word length to be programmable (from 2 to 28 data bits). A frame consists of three bits for sync followed by the data word (2 to 28 data bits) followed by one bit of parity, thus, the frame length will vary from 6 to 32 bit periods. This chip also allows selection of either even or odd parity for the Encoder and Decoder separately. This integrated circuit is fully guaranteed to support the 1MHz data rate of MIL-STD-1553 over both temperature and voltage. For high speed applications the 15531B will support a 2.5 Megabit/sec data rate. The HD-15531/883 can also be used in many party line digital data communications applications, such as a local area network or an environmental control system driven from a single twisted pair or fiber optic cable throughout a building.
Features
· This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. · Support of MIL-STD-1553 · Data Rate (15531B) . . . . . . . . . . . . . . . 2.5 Megabit/Sec · Data Rate (15531) . . . . . . . . . . . . . . . . 1.25 Megabit/Sec · Variable Frame Length to 32-Bits · Sync Identification and Lock-In · Separate Manchester II Encode, Decode · Low Operating Power . . . . . . . . . . . . . . . . . 50mW at 5V
Ordering Information
PACKAGE CERDIP TEMPERATURE RANGE -55oC to +125oC 1.25MBIT/SEC HD1-15531/883 2.5MBIT/SEC HD1-15531B/883 PKG. NO. F40.6
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
File Number
2962.1
5-170
HD-15531/883 Pinout
HD-15531/883 (CERDIP) TOP VIEW
VCC VALID WORD TAKE DATA' TAKE DATA SERIAL DATA OUT SYNCHR DATA SYNCHR DATA SEL SYNCHR CLK DECODER CLK 1 2 3 4 5 6 7 8 9 40 COUNT C1 39 COUNT C4 38 DATA SYNC 37 ENCODER CLK 36 COUNT C3 35 NC 34 ENCODER SHIFT CLK 33 SEND CLK IN 32 SEND DATA 31 ENCODER PARITY SEL 30 SYNC SEL 29 ENCODER ENABLE 28 SERIAL DATA IN 27 BIPOLAR ONE OUT 26 OUTPUT INHIBIT 25 24 BIPOLAR ZERO OUT
SYNCHR CLK SEL 10 BIPOLAR ZERO IN 11 BIPOLAR ONE IN 12 UNIPOLAR DATA IN 13 DECODER SHIFT CLK 14 TRANSITION SEL 15 NC 16 COMMAND SYNC 17 DECODER PARITY SEL 18 DECODER RESET 19 COUNT C0 20
÷ 6 OUT
23 COUNT 2 22 MASTER RESET 21 GND
Block Diagrams
ENCODER
21 22 33 24
GND MASTER RESET SEND CLK IN 6 OUT
VCC OUTPUT INHIBIT
1
26
÷2 ÷6
CHARACTER FORMER
27
BIPOLAR ONE OUT BIPOLAR ZERO OUT
25
37
ENCODER CLK
BIT COUNTER 32 20 C0 40 C1 23 C2 36 C3 39 C4 34 28 29 30 31
SEND DATA
SERIAL DATA IN
SYNC SELECT ENCODER PARITY SELECT
ENCODER SHIFT CLK
ENCODER ENABLE
5-171
HD-15531/883 Block Diagrams
(Continued) DECODER
7 8
SYNCHRONOUS DATA SELECT UNIPOLAR DATA IN BIPOLAR ONE IN BIPOLAR ZERO IN 13 12 11 TRANSITION FINDER
SYNCHRONOUS DATA 4 TAKE DATA COMMAND DATA SYNC 5 SERIAL DATA OUT VALID WORD PARITY SELECT DECODER SHIFT CLK
DATA SELECT GATE
CHARACTER IDENTIFIER
17 38
DECODER CLK DECODER CLK SELECT SYNCHRONOUS CLK SYNCHRONOUS CLK SELECT MASTER RESET
9 15 SYNCHRONIZER 8
CLOCK SELECT DATA
BIT RATE CLK
2 PARITY 16 CHECK
14 10 22
DECODER RESET
19
BIT COUNTER 23 C1 36 C2 39 C3 C4
3
TAKE DATA
20 40 C0
5-172
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