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Part: HI4P0201-5
Category:
Analog & Mixed-Signal Processing
Description: Dual/quad Spst, CMOS Analog Switches
Company: Intersil Corporation
Datasheet: Download HI4P0201-5 datasheet File size : 23 kB
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Datasheet text preview:
HI-200, HI-201
Da ta Sh eet O cto b er 199 9 Fi l e N u m b er 31 21. 4
Dual/Quad SPST, CMOS Analog Switches itle I0, 1) bt ua l/ ad ST, OS aitch utho ) eyrds terrpoion, inctor, itch OS PST, DT, ST, DT, eo, ET, alog itch, anl
HI-200/HI-201 (dual/quad) are monolithic devices comprising independently selectable SPST switches which feature fast switching speeds (HI-200 240ns, and HI-201 185ns) combined with low power dissipation (15mW at 25oC). Each switch provides low "ON" resistance operation for input signal voltage up to the supply rails and for signal current up to 80mA. Rugged DI construction eliminates latch-up and substrate SCR failure modes. All devices provide break-before-make switching and are TTL and CMOS compatible for m aximum application versatility. HI-200/HI-201 are ideal components for use in high frequency analog switching. Typical applications include signal path sw itching, sample and hold circuit, digital filters, and operational amplifier gain switching networks.
Features
· Analog Voltage Range . . . . . . . . . . . . . . . . . . . . . . . ±15V · Analog Current Range . . . . . . . . . . . . . . . . . . . . . . . 80mA · Turn-O n Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240ns · Low rON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 · Low Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . 15mW · TTL/CM OS Compatible
Applications
· High Frequency Analog Switching · Sample and Hold Circuits · Digital Filters · Operational Amplifier Gain Switching Networks
Ordering Information
P ART NUMBER HI1-0200-5 HI2-0200-5 HI3-0200-5 HI1-0201-2 HI1-0201-4 HI1-0201-5 HI3-0201-5 HI4P0201-5 HI9P0201-5 HI9P0201-9 TEMPERATURE RANGE ( oC) 0 to 75 0 to 75 0 to 75 -55 to 125 -2 5 t o 8 5 0 to 75 0 to 75 0 to 75 0 to 75 -4 0 t o 8 5 PACKAGE 14 Ld CERDIP 10 P in Metal Can 14 Ld PDIP 16 Ld CERDIP 16 Ld CERDIP 16 Ld CERDIP 16 Ld PDIP 20 Ld PLC C 16 Ld SOIC 16 Ld SOIC PKG. NO.
Functional Diagram
V+
F14.3 T10.B E14.3 F16.3 F16.3 F16.3 E16.3 N20.35 M16.15 M16.15 1 LOGIC 0
LOGIC INPUT
V RE F INPUT S O URCE GATE
REFERENCE, LEVEL SHIFTER, AND DRIVER
SWITCH CELL
GATE
DRAIN OUTPUT
V-
TRUTH TABLE HI-200 ON OFF HI- 201 ON OFF
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2001, All Rights Reserved
HI-200, HI-201 Pinouts
(Switches Shown For Logic "1" Input) HI-201 (CERDIP, PDIP, SOIC) TOP VIE W
OUT1 A1 1 16 A2 15 OUT2 14 IN2 13 V+ 12 VREF 11 IN3 10 OUT3 9 A3 IN1 VNC GND IN4 4 5 6 7 8 9 OUT4 10 A4 11 NC 12 A3 13 OUT3
HI- 200 (C ERDIP, PDIP) TOP VIEW
A2 1 NC 2 GND 3 NC 4 IN2 5 OUT2 6 V- 7 14 A1 13 NC 12 V+ 11 NC 10 IN1 9 O UT 1 8 VREF
HI-201 (PLCC) TOP VIE W
OUT2 19 18 IN2 17 V+ 16 NC 15 VREF 14 IN3 NC 1
A1
O UT 1 2 IN1 3
3
2
20
V- 4 G ND IN4 5 6
O UT 4 7 A4 8
HI-200 ( ME TAL CAN) TOP VIEW
V+ 10 A1 A2 2 1 9 IN1 8 7 4 5 O UT 2 6 VO UT 1 VREF
GND 3 IN2
Schematic Diagrams
TTL/CMOS REFE RENCE CIRCUIT VREF CELL HI-200
V+ R6 R2 5K QP1 QP 4 Q N1 D3 R3 2 4.2K QN2 R4 5 .4K R5 7 .9K MN15 VGN D G ND MN16 M N1 7 R7 1 00K MN14 D3 30 0 QP 2 QP3 Q N4 MP13 QP 5 TO P2 VREF R2 5K QP1 QP4 Q N1 R3 24 .2K Q N2 R4 5.4 K R5 7.9 K MN15 VMN16 MN17 MN14 MP14 Q N3 QP6 R7 100K VLL QP2 QP3 QN4 MP13 QP5 TO P2 VREF V+ R6 60 0
TTL/CMOS REFERENCE CIRCUIT VREF CELL HI-201
V LL GND
G ND
2
A2
HI-200, HI-201 Schematic Diagrams
(Cont inued) SWITCH CELL
A' QN11
V+
Q N1 2
INPUT
QP11
QN13
OUTPUT
V-
QP12 A'
D IGITAL INP UT BUFFER AND LE VEL SHIFTER
V+
QP 3 QP1
QP5 QP 4 A'
V+
QN1 QP7
D1 TO VLL TO VREF 2 00 D2 QP2 A V-
QP6
QP8
QP9
QP10
Q N8 QN6 QN7
QN9
QN10
A' QN2 Q N4 Q N5
Q N3
V-
3
Others parts begin by hi
HI-1 HI-2 HI-3 HI-4 HI-5 HI-6 HI-7 HI-8 HI-9 HI-10 HI-11
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