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Part: HS0-565BRH-Q
Category:
Power Management
-> broadband power
Description: Radiation Hardened High Speed, Monolithic Digital-to-analog Converter
Company: Intersil Corporation
Datasheet: Download HS0-565BRH-Q datasheet File size : 127 kB
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HS- 565BRH
Da ta Sheet J an ua r y 2003 FN 4 6 07 . 3
Radiation Hardened High Speed, Monolithic Digital-to-Analog Converter
The HS-565BRH is a fast, radiation hardened 12-bit current output, digital-to-analog converter. This part replaces the HS-565ARH, which is no longer available. The monolithic chip includes a precision voltage reference, thin-film R-2R ladder, reference control amplifier and twelve high-speed bipolar current switches. The Intersil Corporation Dielectric Isolation process provides latch-up free operation while minimizing stray capacitance and leakage currents, to produce an excellent combination of speed and accuracy. Also, ground currents are minimized to produce a low and constant current through the ground terminal, which reduces error due to code-dependent ground currents. HS-565BRH die are laser trimmed for a maximum integral nonlinearity error of ±0.25 LSB at 25oC. In addition, the low noise buried zener reference is trimmed both for absolute value and minimum temperature coefficient. Specifications for Rad Hard QML devices are controlled by the Defense Supply Center in Columbus (DSCC). The SMD numbers listed here must be used when ordering. Detailed Electrical Specifications for these devices are contained in SMD 5962-96755. A "hot-link" is provided on our website for downloading.
Features
· Electrically Screened to SMD # 5962-96755 · QML Qualified per MIL-PRF-38535 Requirements · Total Dose . . . . . . . . . . . . . . . . . . . . . 100 krad (Si) (Max) · DAC and Reference on a Single Chip · Pin Compatible with AD-565A and HI-565A · Very High Speed: Settles to 0.50 LSB in 500ns Max · Monotonicity Guaranteed Over Temperature · 0.50 LSB Max Nonlinearity Guaranteed Over Temperature · Low Gain Drift (Max., DAC Plus Reference) . . . . . . . . . . . . . . .50ppm/oC · ±0.75 LSB Accuracy Guaranteed Over Temperature (±0.125 LSB Typical at 25oC)
Applications
· High Speed A/D Converters · Precision Instrumentation · Signal Reconstruction
Functional Diagram
REF OUT VCC 4 3 + 10V IREF 0.5mA 3.5K 3K 7 -VEE 12 PWR G ND 24 . . . 13 MSB LSB + DAC IO (4X IREF X CODE) 2.5K 9.95K 5K 9 BIP. OFF. 8 5K 11 20V SPAN 10V SPAN OUT
Ordering Information
ORDERING NUMBER 59 62R9675502V 9A 59 62R9675502V JC 59 62R9675502V XC HS9-565BRH/PROTO INTERNAL MKT. NUMBER HS0-565BRH-Q HS1-565BRH-Q HS9-565BRH-Q H S9-565B RH/ PRO T O TEMP. RANGE (oC) 25 -55 to 125 -55 to 125 -55 to 125
REF IN
6 19.95K
10
REF 5 GND
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1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
HS-565BRH Pinouts
HS 1-565BRH MIL-STD-1835 CDIP2-T24 (SBDIP) TOP VIEW
NC 1 NC 2 VCC 3 REF OUT 4 REF GND 5 REF IN 6 -VEE 7 BIPOLAR RIN 8 IDAC OUT 9 10V SPAN 10 20V SPAN 11 PWR GND 12 24 BIT 1 IN (MSB) 23 BIT 2 IN 22 BIT 3 IN 21 BIT 4 IN 20 BIT 5 IN 19 BIT 6 IN 18 BIT 7 IN 17 BIT 8 IN 16 BIT 9 IN 15 BIT 10 IN 14 BIT 11 IN 13 BIT 12 IN (LSB)
HS 9-565BRH MIL-STD-1835 CDFP4-F24 (CERAMIC FLATPACK) TOP VIEW
NC NC VCC REF OUT REF GND REF IN -VEE BIPOLAR RIN IDAC OUT 10V SPAN 20V SPAN PWR GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 BIT 1 IN (MSB) BIT 2 IN BIT 3 IN BIT 4 IN BIT 5 IN BIT 6 IN BIT 7 IN BIT 8 IN BIT 9 IN BIT 10 IN BIT 11 IN BIT 12 IN (LSB)
2
HS-565BRH Burn-In Bias Circuit
1 NC +15V D1 C1 2 NC 3 VCC 4 REF OUT 5 REF GND -15V D2 +10V D3 C3 C2 6 REF IN 7 -VEE 8 BIP OFF 9 OUT BIT 1 24 BIT 2 23 BIT 3 22 BIT 4 21 BIT 5 20 BIT 6 19 BIT 7 18 BIT 8 17 BIT 9 16 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11
Definitions of Specifications
Digital Inputs
The HS-565BRH accepts digital input codes in binary format and may be user connected for any one of three binary codes. Straight binary, Two's Complement (see note below), or Offset Binary, (See Operating Instructions).
DIGITAL INPUT MSB...LSB 000 .... 000 100 .... 000 111 .... 111 011 .... 111 STRAIGHT BINARY Z e ro 0.50 FS +FS - 1LSB 0.50 FS - 1LSB ANALOG OUTPUT OFFSET BINARY -FS (Full Scale) Z e ro +FS - 1LSB Zero - 1LSB (NO T E) TWO'S COMPLEMENT Z e ro -F S Zero - 1LSB +FS - 1LSB
10 10V SPAN BIT 10 15 11 20V SPAN BIT 11 14 12 PWR GND BIT 12 13
NOTE: Invert MSB with external inverter to obtain Two's Complement Coding NOTES: D1 = D2 = D3 = IN4002 or Equivalent F0 to F11: VIH = 5.0V ±0.5V VIL = 0.0V ±0.5V F0 = 100kHz ±10% (50% Duty Cycle) F1 = F0/2 F7 = F0/128 F2 = F0/4 F8 = F0/256 F3 = F0/8 F9 = F0/512 F4 = F0/16 F10 = F0/1024 F5 = F0/32 F11 = F0/2048 F6 = F0/64
Accuracy
Nonlinearity - Nonlinearity of a D/A converter is an important measure of its accuracy. It describes the deviation from an ideal straight line transfer curve drawn between zero (all bits OFF) and full scale (all bits ON). Differential Nonlinearity - For a D/A converter, it is the difference between the actual output voltage change and the ideal (1 LSB) voltage change for a one bit change in code. A Differential Nonlinearity of ±1 LSB or less guarantees monotonicity; i.e., the output always increases and never decreases for an increasing input.
Radiation Bias Circuit
1 NC +15V 2 NC 3 VCC 4 REF OUT 5 REF GND -15V 6 REF IN 7 -VEE 8 BIP OFF +10V 9 OUT BI T 1 2 4 BI T 2 2 3 BI T 3 2 2 BI T 4 2 1 BI T 5 2 0 BI T 6 1 9 BI T 7 1 8 BI T 8 1 7 BI T 9 1 6 +5V
Settling Time
Settling time is the time required for the output to settle to within the specified error band for any input code transition. It is usually specified for a full scale or major carry transition, settling to within 0.50 LSB of final value.
Drift
Gain Drift - The change in full scale analog output over the specified temperature range expressed in parts per million of full scale range per oC (ppm of FSR/oC). Gain error is measured with respect to 25oC at high (TH) and low (TL) temperatures. Gain drift is calculated for both high (TH 25oC) and low ranges (25oC - TL) by dividing the gain error by the respective change in temperature. The specification is the larger of the two representing worst case drift. Offset Drift - The change in analog output with all bits OFF over the specified temperature range expressed in parts per million of full scale range per oC (ppm of FSR/oC). Offset error is measured with respect to 25oC at high (TH) and low (TL) temperatures. Offset drift is calculated for both high (TH - 25oC) and low (25oC - TL) ranges by dividing the offset error by the respective change in temperature. The specification given is the larger of the two, representing worst case drift.
10 10V SPAN BIT 10 15 11 20V SPAN BIT 11 14 12 PWR GND BIT 12 13
NOTE: Power Supply Levels are ±0.5V
3
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