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Part: HS0-RTX2010RH-Q
Category:
Microcontrollers
Description: Radiation Hardened Real Time Express Microcontroller
Company: Intersil Corporation
Datasheet: Download HS0-RTX2010RH-Q datasheet File size : 127 kB
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Datasheet text preview:
HS-RTX2010RH
D a ta Sheet M a rch 2000 F i l e Number 3961.3
Radiation Hardened Real Time ExpressTM Microcontroller
The HS-RTX2010RH is a radiation-hardened 16-bit microcontroller with on-chip timers, an interrupt controller, a multiply-accumulator, and a barrel shifter. It is particularly well suited for space craft environments where very high speed control tasks which require arithmetically intensive calculations, including floating point math to be performed in hostile space radiation environments. This processor incorporates two 256-word stacks with multitasking capabilities, including configurable stack par titioning and over/underflow control. Instruction execution times of one or two machine cycles are achieved by utilizing a stack oriented, multiple bus architecture. The high performance ASIC Bus, which is unique to the RTX product, provides for extension of the microcontroller architecture using off-chip hardware and application specific I/O devices. RTX Microcontrollers support the C and Forth programming languages. The advantages of this product are further enhanced through third party hardware and software support. Combined, these features make the HS-RTX2010RH an extremely powerful processor serving numerous applications in high performance space systems. The HS-RTX2010RH has been designed for harsh space radiation environments and features outstanding Single Event Upset (SEU) resistance and excellent total dose response. Specifications for Rad Hard QML devices are controlled by the Defense Supply Center in Columbus (DSCC). The SMD numbers listed here must be used when ordering. Detailed Electrical Specifications for these devices are contained in SMD 5962-95635. A "hot-link" is provided on our homepage for downloading. www.intersil.com/spacedefense/space.asp
Features
· Electrically Screened to SMD # 5962-95635 · QML Qualified per MIL-PRF-38535 Requirements · Fast 125ns Machine Cycle · 1.2µM TSOS4 CMOS/SOS Process · Total Dose Capability . . . . . . . . . . . . . . . . . . 300KRad(Si) · Single Event Upset Critical LET . . . . . . . >120MeV/mg/cm2 · Single Event Upset Error Rate . . . . <1 x 10-10 Errors/Bit-Day (Note) · -55oC - 125oC, 5V ±10% Operation · Single Cycle Instruction Execution · Fast Arithmetic Operations - Single Cycle 16-Bit Multiply - Single Cycle 16-Bit Multiply Accumulate - Single Cycle 32-Bit Barrel Shift - Hardware Floating Point Support · C Software Development Environment · Direct Execution of Fourth Language · Single Cycle Subroutine Call/Return · Four Cycle Interrupt Latency · On-Chip Interrupt Controller · Three On-Chip 16-Bit Timer/Counters · Two On-Chip 256 Word Stacks · ASIC BusTM for Off-Chip Architecture Extension · 1 Megabyte Total Address Space · Word and Byte Memory Access · Fully Static Design - DC to 8MHz Operation · 84 Lead Quad Flat Package or 85 Pin Grid Array · Third Party Software and Hardware Development Systems
NOTE: Single Event Upset error rates are Adams 10% worst case environment under worst case conditions for upset.
Ordering Information
ORDERING NUMBER 5962F9563501QXC 5962F9563501QYC 5962F9563501V9A 5962F9563501VXC 5962F9563501VYC INTERNAL MKT. NUMBER HS8-RTX2010RH-8 HS9-RTX2010RH-8 HS0-RTX2010RH-Q HS8-RTX2010RH-Q HS9-RTX2010RH-Q TEMP. RANGE (oC) 55 to 125 55 to 125 25 55 to 125 55 to 125 55 to 125 55 to 125
Applications
· Space Systems Embedded Control · Digital Filtering · Image Processing · Scientific Instrumentation · Optical Systems · Control Systems · Attitude/Orbital Control
HS8-RTX2010RH/Proto HS8-RTX2010RH/Proto HS9-RTX2010RH/Proto HS9-RTX2010RH/Proto
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 2000 Real Time ExpressTM, RTXTM, and ASIC BusTM are trademarks of Intersil Corporation.
HS-RTX2010RH Block Diagram
OFF CHIP PERIPHERALS MAIN MEMORY
CONTROL INPUTS
CLOCK AND CONFIGURATION CONTROL
HS-RTX2010RH
ASIC BUS INTERFACE MEMORY BUS INTERFACE
INTERRUPT INPUTS
INTERRUPT CONTROL
MEMORY PAGE CONTROL 256-WORD RETURN STACK
TIMER INPUTS
TIMER/ COUNTERS
RTX CORE PROCESSOR
256-WORD PARAMETER STACK
STACK CONTROLLERS
BARREL SHIFTER MAC
Pinouts
HS8-RTX2010RH MIL-STD-1835 CMGA3-P85C
A B C D E F G H J K L L K J H G F E D C B A 11 MA16 MA19 GND UDS PCLK MD01 MD02 GND MD06 MD07 MD08 10 MD11 MD09 VDD MD05 MD03 NEW BOOT LDS MA18 MA17 MA14 MA14 MA17 MA18 LDS BOOT NEW MD03 MD05 VDD MD09 MD11 9 MD12 MD10 8 MD14 MD13 7 GA00 MD15 GA01 HS-RTX2010RH 6 TCLK GND GA02 5 INTA 4 VDD 3 E I2 NMI E I1 E I4 GD14 GD11 GD10 INTSUP TOP VIEW PINS DOWN MA08 MA07 MA11 MA11 MA07 MA08 MA04 MA05 MA06 MA06 MA05 MA04 MA02 MA03 MA03 MA02 GD01 MA01 MA01 GD01 GD10 GD11 GD14 INTSUP NMI INTA 4 ALIGN. PIN E I1 VDD 3 E I4 E I2 2 GD00 GD02 GD03 GD06 GD08 GD12 GD13 GIO WAIT RESET E I3 1 E I5 A PIN A1 ICLK GR/W GD15 GND GD07 GD09 VDD GD05 GD04 GND B C D E F G H J K L 1 GND GD04 GD05 VDD GD09 GD07 GND GD15 GR/W ICLK E I5 L K J H G F E D C B A PIN A1 MD04 MD00 MR/W MA15 VDD VDD MA13 MA12 GND MA10 MA09 MA09 MA10 GND BOTTOM VIEW PINS UP GA02 GND TCLK 5 GA01 MD15 GA00 6 MA15 MR/W MD00 MD04 MD10 MD12 8 MA12 MA13 MD13 MD14 7 9 10
11 MD08 MD07 MD06 GND MD02 MD01 PCLK UDS GND MA19 MA16
2 E I3 RESET WAIT GIO GD13 GD12 GD08 GD06 GD03 GD02 GD00
NOTE: An overbar on a signal name represents an active LOW signal.
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HS-RTX2010RH Pinouts
(Continued) HS9-RTX2010RH (LEAD LENGTH NOT TO SCALE) SEE INTERSIL OUTLINE R84.A
EI5 EI4 EI3 EI2 EI1 VDD INTSUP NMI INTA TCLK GA02 GA01 GA00 MD15 GND MD14 MD13 MD12 MD11 MD10 MD09 RESET WAIT ICLK GR/W GIO GD15 GD14 GD13 GND GD12 GD11 GD10 GD09 GD08 GD07 VDD GD06 GD05 GD04 GD03 GND 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54
HS-RTX2010RH TOP VIEW
MD08 VDD MD07 MD06 MD05 GND MD04 MD03 MD02 MD01 MD00 MR/W PCLK BOOT NEW UDS LDS GND MA19 MA18 MA17
NOTE: An overbar on a signal name represents an active LOW signal.
PGA And CQFP Pin / Signal Assignments
CQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 PGA PIN C6 A6 A5 B5 C5 A4 B4 A3 A2 B3 A1 B2 C2 B1 C1 D2 D1 E3 E2 E1 F2 F3 G3 SIGNAL NAME GA02 TCLK INTA NMI INTSUP VDD EI1 EI2 EI3 EI4 EI5 RESET WAIT ICLK GR/W GIO GD15 GD14 GD13 GND GD12 GD11 GD10 TYPE Output; Address Bus Output Output Input Input Power Input Input Input Input Input Input Input Input Output Output I/O; Data Bus I/O; Data Bus I/O; Data Bus Ground I/O; Data Bus I/O; Data Bus I/O; Data Bus
GD02 GD01 GD00 MA01 MA02 MA03 MA04 MA05 MA06 MA07 MA08 GND MA09 MA10 MA11 MA12 MA13 VDD MA14 MA15 MA16
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
PGA And CQFP Pin / Signal Assignments
CQFP 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 PGA PIN G1 G2 F1 H1 H2 J1 K1 J2 L1 K2 K3 L2 L3 K4 L4 J5 K5 L5 K6 J6 J7 L7 K7 SIGNAL NAME GD09 GD08 GD07 VDD GD06 GD05 GD04 GD03 GND GD02 GD01 GD00 MA01 MA02 MA03 MA04 MA05 MA06 MA07 MA08 GND MA09 MA10
(Continued) TYPE
I/O; Data Bus I/O; Data Bus I/O; Data Bus Power I/O; Data Bus I/O; Data Bus I/O; Data Bus I/O; Data Bus Ground I/O; Data Bus I/O; Data Bus I/O; Data Bus Output; Address Bus Output; Address Bus Output; Address Bus Output; Address Bus Output; Address Bus Output; Address Bus Output; Address Bus Output; Address Bus Ground Output; Address Bus Output; Address Bus
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