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Details, datasheet, quote on part number:HSP43124PC-33
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Datasheet text preview:
HSP43124
Data Sheet May 1999 File Number
3555.6
Serial I/O Filter
The Serial I/O Filter is a high performance filter engine that is ideal for off loading the burden of filter processing from a DSP microprocessor. It suppor ts a variety of multistage filter configurations based on a user programmable filter and fixed coefficient halfband filters. These configurations include a programmable FIR filter of up to 256 taps, a cascade of from one to five halfband filters, or a cascade of halfband filters followed by a programmable FIR. The half band filters each decimate by a factor of two, and the FIR filter decimates from one to eight. When all six filters are selected, a maximum decimation of 256 is provided. For digital tuning applications, a separate multiplier is provided which allows the incoming data stream to be multiplied, or mixed, by a user supplied mix factor. A two pin interface is provided for serially loading the mix factor from an external source or selecting the mix factor from an onboard ROM. The on-board ROM contains samples of a sinusoid capable of spectrally shifting the input data by one quar ter of the sample rate, FS/4. This allows the chip to function as a digital down converter when the filter stages are configured as a low-pass filter. The serial interface for3- input and output data is compatible with the serial ports of common DSP microprocessors. Coefficients and configuration data are loaded over a bidirectional eight bit interface.
Features
· 45MHz Clock Rate · 256 Tap Programmable FIR Filter · 24-Bit Data, 32-Bit Coefficients · Cascade of up to 5 Half Band Filters · Decimation from 1 to 256 · Two Pin Interface for Down Conversion by FS/4 · Multiplier for Mixing or Scaling Input with an External Source · Serial I/O Compatible with Most DSP Microprocessors
Applications
· Low Cost FIR Filter · Filter Co-Processor · Digital Tuner
Ordering Information
PART NUMBER HSP43124PC-45 HSP43124PC-33 HSP43124SC-45 HSP43124SC-33 HSP43124SI-40 TEMP. RANGE (oC) 0 to 70 0 to 70 0 to 70 0 to 70 -40 to 85 PACKAGE 28 Ld PDIP 28 Ld PDIP 28 Ld SOIC 28 Ld SOIC 28 Ld SOIC PKG. NO. E28.6 E28.6 M28.3 M28.3 M28.3
Block Diagram
INPUT FORMATTER
OUTPUT FORMATTER
DIN SCLK SYNCIN MXIN SYNCMX HALF BAND FILTER #1 HALF BAND FILTER #2 HALF BAND FILTER #5
PROGRAMMABLE FIR FILTER
DOUT SYNCOUT CLKOUT
CONTROL INTERFACE
A0-2
C0-7
WR
RD
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
FSYNC
FCLK
HSP43124 Pinout
28 LEAD PDIP, SOIC TOP VIEW
SCLK 1 SYNCIN 2 GND 3 MXIN 4 SYNCMX 5 FSYNC 6 VCC 7 FCLK 8 WR 9 RD 10 A0 11 A1 12 A2 13 VCC 14
28 DIN 27 DOUT 26 SYNCOUT 25 CLKOUT 24 VCC 23 C7 22 C6 21 C5 20 C4 19 GND 18 C3 17 C2 16 C1 15 C0
2
HSP43124 Pin Description
NAME VCC GND DIN TYPE I +5V Power Supply Ground Serial Data Input. The bit value present on this input is sampled on the rising edge of SCLK. A "HIGH" on this input represents a "1", and a low on this input represents "0". The word format and operation of serial interface are contained in the Data Input Section. Data Sync. The HSP43124 is synchronized to the beginning of a new data word on DIN when SCLK samples SYNCIN "HIGH" one SCLK before the first bit of the new word. NOTE: SYNCIN should not maintain a "HIGH" state for longer than one SCLK cycle. Serial Input CLK. The rising edge of SCLK clocks data on DIN and MXIN into the par t. The following signals are synchronous to this clock: DIN, SYNCIN, MXIN, SYNCMX. Mix Factor Input. MXIN is the serial input for the mix factor. It is sampled on the rising edge of SCLK. A "HIGH" on this input represents a "1", and a low on this input represents "0". Also used to specify the Weaver Modulator ROM output as a par t of the two pin FS/4 down conversion interface. Details on word format and operation are contained in the Mix Factor Section. Mix Factor Sync. The HSP43124 is synchronized to the beginning of a serially input mix factor when SCLK samples SYNCMX "HIGH" one SCLK before the first bit of the new mix factor. NOTE: SYNCMX should only pulse "HIGH" for one SCLK cycle. Also used to specify Weaver Modulator ROM output as a part of the two pin FS/4 down conversion interface. Filter Clock. The filter clock determines the processing speed of the Filter Compute Engine. Clock rate requirements on FCLK for par ticular filter configurations is discussed in the Filter Compute Engine Section. This clock may be asynchronous to the serial input clock (SCLK). FSYNC is synchronous to this clock. Filter Sync. This input, when sampled low by the rising edge of FCLK, resets the filter compute engine so that the data sample following the next SYNCIN cycle is the first data sample into the filter structure. If a data stream is currently being input, the current sum of products and the input data are "canceled" and the DIN pin is ignored until the next SYNCIN cycle occurs. Write. The falling edge of WR loads data present on C0-7 into the configuration or coefficient register specified by the address on A0-2. The WR signal is asynchronous to all other clocks. NOTE: WR should not be low when RD is low. Read. The falling edge of RD accesses the control registers or coefficient RAM addressed by A0-2 and places the contents of that memor y location on C0-7. When RD retur ns "HIGH" the C0-7 bus functions as an input bus. The RD pin is asynchronous to all other clocks. NOTE: RD should not be low when WR is low. Address Bus. The A0-2 inputs are decoded on the falling edge of both RD and WR. Table 1 shows the address map for the control registers. Control and Coefficient bus. This bidirectional bus is used to access the control registers and coefficient RAM. Output Clock. Programmable bit clock for serial output. NOTE: Assertion of FSYNC initializes CLKOUT to a high state. Output Data Sync. SYNYOUT is asser ted HIGH for one CLKOUT cycle before the first bit of a new output sample is available on DOUT. Serial Data Output. The bit stream is synchronous to the rising edge of CLKOUT. (See the Serial Output Formatter section for additional details.) DESCRIPTION
SYNCIN
I
SCLK
I
MXIN
I
SYNCMX
I
FCLK
I
FSYNC
I
WR
I
RD
I
A0-2
I
C0-7 CLKOUT
I/O O
SYNCOUT
O
DOUT
O
3
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