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Details, datasheet, quote on part number:HSP43168/883
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Datasheet text preview:
TM
HSP 43168/ 883
D a t a Sheet M ay 1999 F N31 77. 3
Dual FIR Filter
The HSP43168/883 Dual FIR Filter consists of two independent 8-tap FIR filters. Each filter supports decimation from 1 to 16 and provides on-board storage for 32 sets of coefficients. The Block Diagram shows two FIR cells each fed by a separate coefficient bank and one of two separate inputs. The outputs of the FIR cells are either summed or multiplexed by the MUX/Adder. The compute power in the FIR Cells can be configured to provide quadrature filtering, complex filtering, 2-D convolution, 1D/2-D correlations, and interpolating/decimating filters. The FIR cells take advantage of symmetry in FIR coefficients by pre-adding data samples prior to multiplication. This allows an 8-tap FIR to be implemented using only 4 multipliers per filter cell. These cells can be configured as either a single 16-tap FIR filter or dual 8-tap FIR filters. Asymmetric filtering is also supported. Decimation of up to 16 is provided to boost the effective number of filter taps from 2 to 16 times. Further, the Decimation Registers provide the delay necessary for fractional data conversion and 2-D filtering with kernels to 16 x 16. The flexibility of the dual is further enhanced by 32 sets of user programmable coefficients. Coefficient selection may be changed asynchronously from clock to clock. The ability to toggle between coefficient sets further simplifies applications such as polyphase or adaptive filtering. The HSP43168 is a low power fully static design implemented in an advanced CMOS process. The configuration of the device is controlled through a standard microprocessor interface.
Features
· This Circuit is Processed in Accordance to MIL-STD-883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. · Two Independent 8-Tap FIR Filters Configurable as a Single 16-Tap FIR · 10-Bit Data and Coefficients · On-Board Storage for 32 Programmable Coefficient Sets · Up To: 256 FIR Taps, 16 x 16 2-D Kernels, or 10 x 20-Bit Data and Coefficients · Programmable Decimation to 16 · Programmable Rounding on Output · Standard Microprocessor Interface · 33MHz, 25.6MHz Versions
Applications
· Quadrature, Complex Filtering · Correlation · Image Processing · PolyPhase Filtering · Adaptive Filtering
Ordering Information
PART NUMBER HSP43168GM-25/883 HSP43168GM-33/883 TEMP. RANGE ( oC) -55 to 125 -55 to 125 PACKAGE 84 Ld PGA 84 Ld PGA PKG. NO. G84.A G84.A
Block Diagram
CI N0 - 9 A0 - 8 WR CSEL0 - 4 10 9 CONTROL / CONFIGURATION
COEFFICIENT BANK A INA0 - 9 10 FIR CELL A M UX MUX
COEFFICIENT BANK B
FIR CELL B
INB0 - 9/ OUT0 - 8
10
MUX / ADDER 9 OEL OEH 19 OUT9 - 27
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved
HSP43168/883 Pinouts
84 PIN PGA TOP VIEW
11 L K J H G F E D C B A G ND OUT18 10 9 8 7 6 5 INB1 INB2 INB3 4 INB4 G ND 3 INB5 INB7 2 INB6 INB8 INA0 INA3 INA7 INA8 CIN2 INA5 INA9 CIN1 G ND A5 A0 A1 8 A3 A4 7 A6 A2 A7 6 CSEL0 VCC A8 5 CSEL2 CIN9 CIN6 CIN7 1 INB9 INA1 INA2 INA4 INA6 V CC CIN0 CIN3 CIN4 CIN5 L K J H G F E D C B A PIN 'A1' ID
OUT15 OUT14 OUT12 OUT10 OUT11 VCC OUT16 OUT13 V CC OUT9 INB0 OEL
OUT19 OUT17 OUT21 OUT20 OUT24 OUT23 OUT25 OUT27 OUT22 OUT26 OEH VCC TXFR SHFT EN R VRS 11 G ND ACCEN FWRD MUX0 MUX1 WR 10 GND 9 CL K
CSEL1 CSEL3 CSEL4 CIN8 4 3 2 1
84 PIN PGA BOTTOM VIEW
11 A B C D E F RVRS S HF T EN 10 WR 9 GND 8 A1 A0 7 A4 A3 A5 6 A7 A2 A6 5 A8 V CC CSEL0 4 3 2 1 A PIN 'A1' ID B C D E F G
CSEL1 CSEL3 CSEL4 CI N8 CSEL2 CIN9 CIN7 CIN6 G ND CI N5 CI N4 CI N3 CI N0 V CC I NA6
MUX0 MUX1
TXFR FWRD VCC OEH ACCEN G ND CL K
CIN2 INA8 INA7
CIN1 INA9 INA5
OUT27 OUT2 2 OUT26
G OUT24 OUT2 3 OUT25
H J K L
OUT21 OUT2 0 OUT19 OUT1 7 OUT18 G ND 11 V CC OUT16 OUT13 OUT9 V CC OEL INB0 INB 3 INB 2 INB 1 5 GND INB4 4 INB7 INB5 3
INA3 INA0 INB8 INB6 2
I NA4 I NA2 I NA1 I NB9 1
H J
K L
OUT15 OUT14 OUT12 OUT10 OUT11 10 9 8 7 6
2
HSP43168/883 Pin Description
NAM E VCC G ND C IN0-9 A0-8 WR CSEL0-4 INA0- 9 INB0- 9 OUT9-27 PIN NUMBER B5, D11, K10, K7, F1 A9, E10, L11, K4, D2 E1-3, D1, C1-2, B1-3, A1 A5- 8, B6-8, C6-7 A10 A2-4, B4, C5 K 1, J1-2, H1-2, G1-3, F2-3 L1-5, K2-3, K5-6, J5 F9-11, G9-11, H10-11, J10-11, J7, K11, K8-9, L6-10 B11 C1 0 A11 C1 1 B9-10 E9 J6 E11 D1 0 I I I I I I/O O TYPE VCC: +5V power supply pin. Gr ound. Control/Coefficient Data Bus. Processor interface for loading control data and coefficients. CIN0 is the LSB. Control/Coefficient Address Bus. Processor interface for addressing control and Coefficient Registers. A0 is the LSB. Control/Coefficient Write Clock. Data is latched into the Control and Coefficient Registers on the rising edge of WR. Coefficient Select. This input determines which of the 32 coefficient sets are to be used by FIR A and B. This input is registered and CSEL0 is the LSB. Input to FIR A. INA0 is the LSB. Bidirectional Input for FIR B. INB0 is the LSB and is input only. When used as output, INB1-9 is the LSB's of the output bus. 19 MSB's of Output Bus. Data format is either unsigned or two's complement depending on configuration. OUT27 is the MSB. Shift Enable. This active low input enables shifting of data through the Decimation Registers. Forw ard ALU Input Enable. When active low, data from the forward decimation path is input to the ALU's through the "a" input. When high, the "a" inputs to the ALUs are zeroed. Reverse ALU Input Enable. When active low, data from the reverse decimation path is input to the ALU's through the "b" input. When high, the "b" inputs to the ALUs are zeroed. Data Transfer Control. This active low input switches the LIFO being read into the reverse decimation path with the LIFO being written from the forward decimation path (see Figure 1). Adder/Mux Control. This input controls data flow through the output Adder/Mux. Table 3.0 lists the various configurations. Clock. All inputs except those associated with the processor interface (CIN0-9, A0-8, WR) and the output enables (OEL, OEH) are registered by the rising edge of CLK. Output Enable Low. This tristate control enables the LSB's of the output bus to INB1-9 when OEL is low. Output Enable High. This tristate control enables OUT9-27 when OEH is low. Accumulate Enable. This active high input allows accumulation in the FIR Cell Accumulator. A low on this input latches the FIR Accumulator contents into the Output Holding Registers while zeroing the feedback path in the accumulator. DESCR IPTION
SHFTEN FWRD RVRS TXFR MUX0-1 CLK OEL OEH ACCEN
I I I I I I I I I
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