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Details, datasheet, quote on part number:HSP43220/883
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Datasheet text preview:
TM
HSP 43220/ 883
D a t a Sheet M ar ch 1999 F N28 02. 3
Decimating Digital Filter
The HSP43220/883 Decimating Digital Filter is a linear phase low pass decimation filter which is optimized for filtering narrow band signals in a broad spectrum of a signal processing applications. The HSP43220/883 offers a single chip solution to signal processing application which have historically required several boards of ICs. This reduction in component count results in faster development times, as well as reduction of hardware costs. The HSP43220/883 is implemented as a two stage filter structure. As seen in the Block Diagram, the first stage is a High Order Decimation Filter (HDF) which utilizes an efficient decimation (sample rate reduction) technique to obtain decimation up to 1024 through a coarse low-pass filtering process. The HDF provides up to 96dB aliasing rejection in the signal pass band. The second stage consists of a Finite Impulse Response (FIR) decimation filter structured as a transversal FIR filter with up to 512 symmetric taps which can implement filters with sharp transition regions. The FIR can perform further decimation by up to 16 if required, while preserving the 96dB aliasing attenuation obtained by the HDF. The combined total decimation capability is 16,384. The HSP43220/883 accepts 16-bit parallel data in 2's complement format at sampling rates up to 30MSPS. It provides a 16-bit microprocessor compatible interface to simplify the task of programming and three-state outputs to allow the connection of several ICs to a common bus. The HSP43220/883 also provides the capability to bypass either the HDF or the FIR for additional flexibility.
Features
· This Circuit is Processed in Accordance to MIL-STD-883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. · Single Chip Narrow Band Filter with up to 96dB Attenuation · DC to 25.6MHz Clock Rate · 16-Bit 2's Complement Input · 20-Bit Coefficients in FIR · 24-Bit Extended Precision Output · Programmable Decimation up to a Maximum of 16,384 · Standard 16-Bit Microprocessor Interface · Filter Design Software Available DECI·MATETM
Applications
· Very Narrow Band Filters · Zoom Spectral Analysis · Channelized Receivers
Ordering Information
PART NUMBER HSP43220GM-15/883 HSP43220GM-25/883 TEMP. RANGE ( oC) -55 to 125 -55 to 125 PACKAGE 84 Ld PGA 84 Ld PGA PKG. NO. G84.A G84.A
Block Diagram
DECIMA TION UP TO 1024 INPUT CLOCK DATA INPUT CONTROL AND COEFFICIENTS HIGH ORDER DECIMATION FILTER DECIMATION UP TO 16 FIR DECIMATION FILTER FIR CLOCK 24
16 16
DATA OUT DATA READY
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved D ECIMATETM is a trademark of Intersil Corporation. IBM PC, XT, AT, PS/2TM are trademarks of IBM Corporation.
HSP43220/883
Absolute Maximum Ratings
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8V Input, Output Voltage . . . . . . . . . . . . . . . . . . . GND -5V to VCC 0.5V ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
Thermal Resistance (Typical, Note 1) JA ( oC/W) JC (oC/W) PGA Package. . . . . . . . . . . . . . . . . . . . 35 5 Maximum Package Power Dissipation at 125oC PGA Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.52 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 175oC Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
Operating Conditions
Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to 5.5V Temper ature Range. . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Die Characteristics
Number of Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48,250
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air. TABLE 1. D C ELECTRICAL PERFORMANCE SPECIFICATIONS Devices Guaranteed and 100% Tested TEST CONDITIONS VCC = 5.5V VCC - 4.5V IOH = 400µA, VCC = 4.5V (Note 2) IOL = 2.0mA VCC = 4.5V (Note 2) VIN = VCC or GND, VCC = 5.5V VOUT = VCC or GND, VCC = 5.5V VCC = 5.5V VCC = 4.5V VIN = VCC or GND, VCC = 5.5V, Outputs Open f = 15.0MHz, VCC = 5.5V (Note 3) (Note 4) GROUP A SUBGROUPS 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 LIMITS TEMP (oC) -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 MIN 2.2 2.6 -1 0 -1 0 3.0 TYP 0.8 0.4 +10 +10 0.8 500 U NITS V V V V µA µA V V µA
PARAMETER Logical One Input Voltage Logical Zero Input Voltage Output HIGH Voltage Output LOW Voltage Input Leakage Current Output Leakage Current Clock Input High Clock Input Low Standby Power Supply Current
SYMBOL VIH VIL VOH VOL II IO VIHC VILC ICCSB
Operating Power Supply Current Functional Test NOTES :
ICCOP FT
1, 2, 3 7, 8
-55 TA 125 -55 TA 125
-
120 -
mA
2. Interchanging of force and sense conditions is permitted. 3. Operating supply current is proportional to frequency, typical rating is 8mA/MHz. 4. Tested as follows: f = 1MHz, VIH = 2.6, VIL = 0.4, VOH 1.5V, VOL 1.5V, VIHC = 3.4V and VILC = 0.4V.
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HSP43220/883
TABLE 2. A C ELECTRICAL PERFORMANCE SPECIFICATIONS Devices Guaranteed and 100% Tested (N OTES) (NOTE 5) GROUP A SUBGROUPS 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 -15 (15MHz) TEMP (oC) -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 MIN 66 66 26 26 0 4 TCK 8 TCK TCK +10 25 20 0 26 26 28 M AX TFIR -25 35 -25 (25.6MHz) MIN 39 39 16 16 0 4 TCK 8 TCK TCK +10 15 16 0 15 20 24 M AX TFIR -19 20 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
PA RAME TER Input Clock Period FIR Clock Period Clock Pulse Width Low Clock Pulse Width High Clock Skew Between FIR_C LK and CK_IN RE SET Pulse Width Low Recovery Time On RE SET AS TARTIN Pulse Width Low STARTOUT Delay From CK_IN STARTIN Setup to CK _IN Setup Time on DATA_IN Hold Time on All Inputs Write Pulse Width Low Write pulse Width High Setup Time on Address Bus Before the Rising Edge of Write Setup Time on Chip Select Before the Rising Edge of Write Setup Time on Control Bus Before the Rising Edge of Write DA TA_RDY Pulse Width Low DA TA_OUT Delay Relative to FIR_CK DA TA_RDY Valid Delay Relative to FIR_CK DA TA_OUT Delay Relative to OUT_SELH Output Enable to Data Out Valid NOTES :
SYMBOL t CK tFIR tSPWL tSPWH tSK tRSPW tRTRS tAST tSTOD tSTIC tSET tHOLD tWL tWH tSTADD
tSTCS
9, 10, 11
-55 TA 125
28
-
24
-
ns
tSTCB
9, 10, 11
-55 TA 125
28
-
24
-
ns
tDRPWL tFIRDV tFIRDR tOUT tOEV Note 6
9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11
-55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125
2TFIR -20 -
50 35 30 20
2TFIR -10 -
35 25 25 20
ns ns ns ns ns
5. AC Testing: VCC = 4.5V and 5.5V. Inputs are driven at 3.0V for a Logic "1" and 0.0V for a Logic "0". Input and output timing measurements are made at 1.5V for both a Logic "1" and "0". CLK is driven at 4.0V and 0V and measured at 2.0V. 6. Transition is measured at ±200mV from steady state voltage with loading as specified by test load circuit and CL = 40pF.
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