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Details, datasheet, quote on part number:HSP43881
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Datasheet text preview:
HSP4388 1
TM
Da ta Sheet
M a y 1999
FN 2 7 58 . 4
Digital Filter
The HSP43881 is a video speed Digital Filter (DF) designed to efficiently implement vector operations such as FIR digital filters. It is comprised of eight filter cells cascaded internally and a shift and add output stage, all in a single integrated circuit. Each filter cell contains a 8 x 8-bit multiplier, three decimation registers and a 26-bit accumulator. The output stage contains an additional 26-bit accumulator which can add the contents of any filter cell accumulator to the output stage accumulator shifted right by 8 bits. The HSP43881 has a maximum sample rate of 30MHz. The effective multiply accumulate (mac) rate is 240MHz. The HSP43881 DF can be configured to process expanded coefficient and word sizes. Multiple DFs can be cascaded for larger filter lengths without degrading the sample rate or a single DF can process larger filter lengths at less than 30MHz with multiple passes. The architecture permits processing filter lengths of over 1000 taps with the guarantee of no overflows. In practice, most filter coefficients are less than 1.0, making even larger filter lengths possible. The DF provides for 8-bit unsigned or two's complement arithmetic, independently selectable for coefficients and signal data. Each DF filter cell contains three resampling or decimation registers which permit output sample rate reduction at rates of 1/2, 1/3 or 1/4 the input sample rate. These registers also provide the capability to perform 2-D operations such as matrix multiplication and N x N spatial correlations/convolutions for image processing applications.
Features
· Eight Filter Cells · 0MHz to 30MHz Sample Rate · 8-Bit Coefficients and Signal Data · 26-Bit Accumulator Per Stage · Filter Lengths Over 1000 Taps · Expandable Coefficient Size, Data Size and Filter Length · Decimation by 2, 3 or 4
Applications
· 1-D and 2-D FIR Filters · Radar/Sonar · Adaptive Filters · Echo Cancellation · Complex Multiply-Add · Sample Rate Converters
Ordering Information
PART N U MB E R HSP 43881JC-20 HSP 43881JC-25 HSP 43881JC-30 HSP 43881G C-20 HSP 43881G C-25 HSP 43881G C-30 TEMP. RANGE (o C ) 0 to 70 0 to 70 0 to 70 0 to 70 0 to 70 0 to 70 P ACKAGE 84 Ld PLCC 84 Ld PLCC 84 Ld PLCC 85 Ld PGA 85 Ld PGA 85 Ld PGA PKG. NO. N84.1.15 N84.1.15 N84.1.15 G85.A G85.A G85.A
Block Diagram
VC C DIENB CIENB DCM O - 1 ERASE T CCI CIN0 - 7 RESET CL K ADR 0 - 2 RESET CLK SHADD SENBL SENBH 8 5 VSS DIN0 - DIN7 TCS 8 5 8 DF FILTER CELL 0 5 3 MUX ADR0, ADR1, ADR2 2 26 OUT P UT STAGE 2 SUM0 - 25 26 26 8 8 DF FILTER CELL 1 26 8 8 DF FILTER CEL L 2 26 8 8 DF FILTER CEL L 3 26 8 8 DF FILTER CELL 4 26 8 8 DF FILTER CELL 5 26 8 8 DF FILTER CELL 6 26 8 8 DF FILTER CEL L 7 26 T CCO 8 COUT0 - 7 CO ENB
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved
HSP43881 Pinouts
85 PIN GRID ARRAY (PGA) TOP VIEW, PINS DOWN
1 A VSS VC C 2 COENB 3 VCC 4 5 6 DIN6 7 DIN3 8 DIN0 9 T CCI 10 VC C CIN6 11 VSS CI N4
RESET DIN7
B
COUT 7 T CCO E RASE T CS ALIGN PIN
DIN1
DIN2
CIENB
CIN7
C COUT 5 C OUT 6
DIENB
DIN5
DIN4
CIN5
CI N3 VC C
D COUT 3 C OUT 4
CIN2
E COUT 1
VSS
COUT 2
CIN1
CIN0 S E N B L
F G
VSS
COUT 0 S HADD CLK
SUM 0
VC C
VSS
ADR2 DCM 0
SUM1 SUM3 SUM2
H J
ADR1 VC C
A DR0 SUM25 SUM20 SUM17 SUM16
SUM5 SUM4 SUM 7 VSS
K SENBH SUM24
VSS
VC C
SUM19
VSS
SUM15 SUM12 SUM10 SUM8 SUM6
L
DCM1 SUM23 SUM22 SUM21 SUM18 SUM14
VC C
SUM13
VSS
SUM11 SUM9
HSP 43881 TOP VIEW, PINS UP
1 2 3 4 5 6 7 8 9 10 11
L DCM1 K SENBH J VCC H ADR1 G ADR2 F VSS E COUT1 D COUT3 C COUT5 COUT6 B VCC A VSS C O E NB VCC RE S E T DIN7 DIN6 DIN3 DIN0 CIN8 VCC VSS COUT7 COUT8 E RA S E DIN8 DIN1 DIN2 CIENB CIN7 CIN6 CIN4 ALIGN PIN DIENB DIN5 DIN4 CIN5 CIN3 COUT4 CIN2 VCC VSS COUT2 CIN1 CIN0 S E NB L COUT0 SHADD SUM0 VCC VSS DCM0 CLK SUM1 SUM3 SUM2 ADR0 SUM5 SUM4 SUM25 SUM20 SUM17 SUM16 SUM7 VSS SUM24 VSS VCC SUM19 VSS SUM15 SUM12 SUM10 SUM8 SUM6 SUM23 SUM22 SUM21 SUM18 SUM14 VCC SUM13 VSS SUM11 SUM9
2
HSP43881 Pinouts
(Continued) 84 LEAD PLCC PACKAGE BOTTOM VIEW
SHADD SENBH ADDR0 ADDR1 ADDR2 COUT 0 COUT 1 COUT 2 COUT 3 COUT 4 COUT 5 SUM24 SUM25 DCM 1 DCM 0
VCC
CL K
VSS
11 10 SUM23 SUM22 VC C SUM21 SUM20 SUM19 SUM18 VSS SUM17 SUM16 VC C SUM15 SUM14 SUM13 SUM12 VSS SUM11 SUM10 SUM9 SUM8 SUM7 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
9
8
7
6
5
4
3
2
1 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 COUT 6 COUT 7 VSS T CCO COENB VC C ERASE RESET DIENB T CS DIN7 DIN6 DIN5 DIN4 DIN3 DIN2 DIN1 DIN0 CIENB T CCI VC C
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
CIN0
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
SUM6
SUM5
SUM4
SUM3
SUM2
SUM1
SUM0
NOTE: An overbar on a signal name represents an active LOW signal.
3
SENBL
CIN7
VSS
VSS
VCC
VCC
VSS
VCC
VSS
VSS
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