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Details, datasheet, quote on part number:HSP50307
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Datasheet text preview:
®
NO
October 2000
CT T O DU M EN E P R P LA C E T O LE RE O B S EN D ED OM M RE C
HSP50307
Burst QPSK Modulator
Features
· 256 KBPS Data Rate and 128 KBPS Baud Rate · Burst QPSK Modulation · Programmable Carrier Frequency from 8MHz to 15MHz With a Frequency Step Size of 32kHz · = 0.5 Root Raised Cosine (RRC) Filtering For Spectrum Shaping · On-Board Synthesizer · Programmable Output Level From 22 to 62dBmV in 1dB Steps · Programmable Charge Pump Current Control · 62dBmV Differential Output Driver for 75 Cable
Description
The HSP50307 is a mixed signal burst QPSK Modulator for upstream CATV Applications. The HSP50307 demultiplexes and modulates a serial data stream onto an RF Carrier centered between 8 and 15MHz. The signal spectrum is shaped with = 0.5 root raised cosine (RRC) digital filters. On-chip filtering limits spurs and harmonics to levels below -35dBc during transmissions. The output power level is adjustable over a 40dB range in 1dB steps. The maximum differential output level is +62dBmV into 75. A transmitter inhibit function disables the RF output outside the burst interval. The differential output amplifier int7-erfaces to the cable via a transformer. The Block Diagram of the HSP50307 QPSK Modulator is shown below. The HSP50307 consists of a digital control interface, an I/Q generator, a synthesizer, and a quadrature modulator. The data clock is derived from the master clock. The HSP50307 demultiplexes the input data bits into in-phase (I) and quadrature (Q) data streams. The first bit and subsequent alternating bits of the burst are in-phase data. The two data streams are filtered, converted from digital to analog, and low pass filtered to produce the baseband I and Q analog signals.
PKG. NO. M28.3
Applications
· Burst QPSK Modulator · HSP50307EVAL1 Evaluation Board Is Available
Ordering Information
PART NUMBER HSP50307SC TEMP. RANGE (oC) 0 to 70 PACKAGE 28 Ld SOIC
The baseband signals are up-converted to RF in the Quadrature Modulation Section. The synthesizer provides the local oscillator (LO) for the quadrature modulator. The frequency is programmable via the control interface with a resolution of 32kHz. The output of the quadrature modulator is low pass filtered to remove harmonic distortion.
Block Diagram
RCLK VCO_IN VCO_SET PD_OUT RESET C C LK C_EN CDATA TX_EN I TX_DATA DEMUX CONTROL INTERFACE SYNTHESIZER
QUAD GEN
QUADRATURE MODULATOR
I/Q GENERATOR 8RRC 9 D/A LPF
MOD_OUT+ LPF PGA MOD_OUT+ D/A LPF TX_EN
Q
9 8RRC
TXCLK MCLK /100
QBBOUT
IBBOUT
Indicates analog circuitry.
MCLK MUST ALWAYS BE PRESENT FOR PROPER OPERATION
QBBIN
IBBIN
DAC_REF
VCM_REF
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved 1
FN4219.1
HSP50307 Pinout
28 LEAD SOIC TOP VIEW
MCLK 1 TXCLK 2 TX_EN 3 TX_DATA 4 RESET 5 DGND 6 AVCC 7 AGND 8 IBBOUT 9 QBBOUT 10 QBBIN 11 IBBIN 12 DAC_REF 13 VCM_REF 14 28 CCLK 27 CDATA 26 C_EN 25 DVCC 24 RCLK 23 AGND 22 PD_OUT 21 VCO_IN 20 VCO_SET 19 AVCC 18 MOD_OUT17 MOD_OUT+ 16 AVDD 15 AGND
Pin Description
SYMBOL MCLK T X C LK TX_EN TX_DATA RESET TYPE I O I I I Master clock input (25.6MHz). (D) PSK data clock (256kHz) for PSK_DATA_IN. (D) Transmit Enable. When high, the modulator output is enabled. This pin should be high for the entire burst. The signal is extended internally until data has fully exited the part before turning off for spurious free turn on and turn off. (D) 256 KBPS serial data input. (D) Digital Reset Pin (active low). The part is reset immediately on assertion of the reset pin. The output of the part is disabled on the assertion of reset. The part will come out of reset 2 master clock periods after the reset is deasserted. Reprogramming (see Control Interface Section) is needed after deassertion of reset for proper operation. (D) Negative supply for the digital filters and control. (P) Positive supply for the quadrature modulator. AVCC should be tied to +5V analog. (P) Negative supply for the quadrature modulator. AGND is tied to GND. (P) I baseband filtered output. (A) Q baseband filtered output. (A) Q baseband modulator input. (A) I baseband modulator input. (A) D/A reference node. A 0.1µF capacitor to ground is suggested. (A) Modulator common mode reference node. A 0.1µF capacitor to ground is suggested. (A) Negative supply for the cable interface. (P) Positive supply for the cable interface (+9V analog). (P) Positive output drive pin for the cable interface. (A) Negative output drive pin for the cable interface. (A) DESCRIPTION
DGND AVCC AGND IBBOUT QBBOUT QBBIN IBBIN DAC_REF VC M_REF AGND AVDD MOD _ OU T+ MOD_OUT -
I I I O O I I O O I I O O
2
HSP50307 Pin Description
SYMBOL AVCC VCO_SET VCO_IN PD_OUT AGND RC LK DVCC C_EN CDATA CC LK TYPE I I/O I O I I I I I I (Continued) DESCRIPTION Positive supply for the synthesizer (+5V analog). (P) VCO free running frequency set resistor (normally 6.25k). (D) Voltage-controlled oscillator control voltage. (D) Phase/frequency detector output. (D) Negative supply for the synthesizer. (P) Synthesizer reference clock input (2.048MHz). (D) Positive supply for the digital filters and control (+5V digital). (P) Control interface enable for 3 wire interface. See Control Interface Section. (D) Serial data input for 3 wire interface. See Control Interface Section. (D) 3 wire interface clock. See Control Interface Section. (D)
NOTE: (A) = analog, (D) = digital, (P) = power.
Functional Description
The HSP50307 is designed to transmit 256 KBPS data using QPSK modulation on a programmable carrier over 75 cable lines. The incoming 256 KBPS data is first demultiplexed into in-phase (I) and quadrature (Q) data streams. The burst QPSK modulator shapes the two 128 KBPS demultiplexed data streams using interpolateby-8 root-raised cosine (RRC) filters with = 0.5. The resulting 1.024MHz data streams are sent through D/A converters and are then sent through low-pass reconstruction filters for over 40dB image rejection. The baseband analog output and input pins allow the signals to be AC coupled. The returning analog signal is upconverted by an analog quadrature modulator. The control section is configured by loading 23 bits of information via a three-wire interface. These bits configure the DSP filter section, the carrier frequency, the analog synthesizer, and the output driver sections.
0.8 0.7 0.6 COEFFICIENT VALUE 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 1 8 16 24 32 40 TAP NUMBER 48 56 64
FIGURE 1. NORMALIZED IMPULSE RESPONSE OF THE RRC INTERPOLATION FILTER WITH = 0.5
MKR 8.0960MHz -16.83dBm
Digital Filters
The burst QPSK modulator uses an interpolate-by-8 digital RRC filter on both the I and Q data streams. The shaping factor is set to = 0.5. The FIR order of the digital RRC filter is 64. Figure 1 shows the impulse response of the RRC filter. Figure 2 is a spectrum analyzer plot of the modulator output for a baud rate of 128 kbaud and a pseudorandom data pattern. The 128kHz 3dB bandwidth and 192kHz stopband edges are readily apparent.
PEAK LO G 5dB/
REF -15.0 dBm
# AT 60dB
WA SB SC FS CORR
CENTER 8.0960MHz #RES BW 300Hz
VBW 300Hz
SPAN 400.0kHz SWP 13.3s
FIGURE 2. SPECTRUM OF 8.096MHz RANDOM DATA MODULATED CARRIER
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