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Details, datasheet, quote on part number:HSP9501-25
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Datasheet text preview:
HSP9501
TM
D a ta Sheet
J a nu a r y 1999
F i l e Number
2786.4
Programmable Data Buffer
The HSP9501 is a 10-Bit wide programmable data buffer designed for use in high speed digital systems. Two different modes of operation can be selected through the use of the MODSEL input. In the delay mode, a programmable data pipeline is created which can provide 2 to 1281 clock cycles of delay between the input and output data. In the data recirculate mode, the output data path is internally routed back to the input to provide a programmable circular buffer. The length of the buffer or amount of delay is programmed through the use of the 11-bit Length Control Input Por t (LC010) and the Length Control Enable (LCEN). An 11-bit value is applied to the LC0-10 inputs, LCEN is asserted, and the next selected clock edge loads the new count value into the Length Control Register. The delay path of the HSP9501 consists of two registers with a programmable delay RAM between them, therefore, the value programmed into the Length Control Register is the desired length - 2. The range of values which can be programmed into the Length Control Register are from 0 to 1279, which in turn results in an overall range of programmable delays from 2 to 1281. Clock select logic is provided to allow the use of a positive or negative edge system clock as the CLK input to the HSP9501. The active edge of the CLK input is controlled through the use of the CLKSEL input. All synchronous timing (i.e., data setup, hold, and output delays) are relative to the clock edge selected by CLKSEL. An additional clock enable input (CLKEN) provides a means of disabling the internal clock and holding the existing contents temporarily. All outputs of the HSP9501 are three-state outputs to allow direct interfacing to system or multi-use busses. The HSP9501 is recommended for digital video processing or any applications which require a programmable delay or circular data buffer.
Features
· DC to 32MHz Operating Frequency · Programmable Buffer Length from 2 to 1281 Words · Suppor ts Data Words to 10 Bits · Clock Select Logic for Positive or Negative Edge System Clocks · Data Recirculate or Delay Modes of Operation · Expandable Data Word Width or Buffer Length · Three-State Outputs · TTL Compatible Inputs/Outputs · Low Power CMOS
Applications
· Sample Rate Conversion · Data Time Compression/Expansion · Software Controlled Data Alignment · Programmable Serial Data Shifting · Audio/Speech Data Processing Video/Image Processing
Video/Image Processing
· 1-H Delay Line of 910 NTSC, 1135 PAL or 1280 Samples: - High Resolution Monitor Delay Line - Comb Filter Designs - Progressive Scanning Display - TV Standards Conversion - Image Processing
Ordering Information
PART NUMBER HSP9501JC-25 HSP9501JC-32 HSP9501JC-2596 TEMP. RANGE (oC) 0 to 70 0 to 70 0 to 70 PACKAGE 44 Ld PLCC 44 Ld PLCC 44 Ld PLCC Tape and Reel PKG. NO. N44.65 N44.65 N44.65
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000
HSP9501 Pinout
44 LEAD PLCC TOP VIEW
MODSEL 40 CLKSEL CLK EN
LCEN
CLK
LC2
LC3
LC4 42
6
5
4
3
2
1
44
43
41
LC5
NC
NC
DO0 DO1 DO2
7 8 9
39 DI0 38 DI1 37 DI2 36 DI3 35 DI4 34 VCC 33 GND 32 DI5 31 DI6 30 DI7 29 DI8
DO3 10 DO4 11 VCC 12 GND 13 DO5 14 DO6 15 DO7 16 DO8 17
18 DO9
19 OE
20 LC0
21 LC1
22 LC10
23 LC9
24 LC8
25 LC7
26 LC6
27 DI9 DI 0 -9 10 10 10
28 NC
Block Diagram
MODSEL
REGISTER
MUX
CLKSEL CLKEN CLK
CLOCK GENERATOR
REGISTER
11 LC0 -10
REGISTER EN
11 PROGRAMMABLE DELAY RAM 0-1279 DELAYS 10 REGISTER
10
LCEN
10 OE 10 DO0-9
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HSP9501 Pin Descriptions
NAME VCC GND CLK PIN NUMBER 12, 34 TYPE DESCRIPTION The +5V power supply pin. A 0.1µF capacitor between the VCC and GND pin is recommended. The device ground. I Input Clock. This clock signal is used to control the data movement through the programmable buffer. It is also the signal which latches the input data, length control word and mode select. Input setup and hold times with respect to the clock must be met for proper operation. Data Inputs. This 10-bit input port is used to provide the input data. When MODSEL is low, data on the DI0-9 inputs is latched on the clock edge selected by CLKSEL. Data Outputs. This 10-bit port provides the output data from the Internal Delay Registers. Data latched into the DI0-9 inputs will appear at the DO0 9 outputs on the Nth clock cycle, where N is the total delay programmed. Length Control Inputs. These inputs are used to specify the number of clock cycles of delay between the DI0-9 inputs and the DO0-9 outputs. An integer value between 0 and 1279 is placed on the LC0-10 inputs, and the total delay length (N) programmed is the LC0-10 value plus 2. In order to properly load an active length control word, the value must be presented to the LC0-10 inputs and LCEN must be asserted during an active clock edge selected by CLKSEL. Length Control Enable. LCEN is used in conjunction with LC0-10 and CLK to load a new length control word. An 11-bit value is loaded on the LC0-10 inputs, LCEN is asserted, and the next selected clock edge will load the new count value. Since this operation is synchronous, LCEN must meet the specified setup/hold times with respect to CLK for proper operation. Output Enable. This input controls the state of the DO0-9 output port. A low on this control line enables the port for output. When OE is high, the output drivers are in the high impedance state. Internal latching or transfer of data is not affected by this input. Mode Select. This input is used to control the mode of operation of the HSP9501. A low on MODSEL causes the device to latch new data at the DI0-9 inputs on every clock cycle, and operate as a programmable pipeline register. When MODSEL is high, the HSP9501 is in the recirculate mode, and will operate as a programmable length circular buffer. This control signal may be used in a synchronous fashion during device operation, however, care must be taken to ensure the required setup/hold times with respect to CLK are met. Clock Select Control. This input is used to determine which edge of the CLK signal is used for controlling all internal events. A low on CLKSEL selects the negative going edge, therefore, all setup, hold, and output delay times are with respect to the negative edge of CLK. When CLKSEL is high, the positive going edge is selected and all synchronous timing is with respect to the positive edge of the CLK signal. Clock Enable. This control signal can be used to enable or disable the CLK input. When low, the CLK input is enabled and will operate in a normal fashion. A high on CLKEN will disable the CLK input and will "hold'' all internal operations and data. This control signal may also be used in a synchronous fashion, however, setup and hold requirements with respect to CLK must be met for proper device operation. This signal takes effect on the clock following the one that latches it in.
13, 33 1
DIO-9
27, 29-32, 35-39
I
DO0-9
7-11, 14-18
O
LC0-10
20-26, 41-44
I
LCEN
6
I
OE
19
I
MODSEL
40
I
CLKSEL
5
I
CLKEN
2
I
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