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Details, datasheet, quote on part number:ICL7109IDL
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Datasheet text preview:
November 2000
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ICL7109
12-Bit, MicroprocessorCompatible A/D Converter
Features
· 12-Bit Binary (Plus Polarity and Over-Range) Dual Slope Integrating Analog-to-Digital Converter · Byte-Organized, TTL Compatible Three-State Outputs and UART Handshake Mode for Simple Parallel or Serial Interfacing to Microprocessor Systems · RUN/HOLD Input and STATUS Output Can Be Used to Monitor and Control Conversion Timing · True Differential Input and Differential Reference · Low Noise (Typ) . . . . . . . . . . . . . . . . . . . . . . . . 15µVP-P · Input Current (Typ) . . . . . . . . . . . . . . . . . . . . . . . . . .1pA · Operates At Up to 30 Conversions/s · On-Chip Oscillator Operates with Inexpensive 3.58MHz TV Crystal Giving 7.5 Conversions/s for 60Hz Rejection. May Also Be Used with An RC Network Oscillator for Other Clock Frequencies
Description
The ICL7109 is a high performance, CMOS, low power integrating A/D converter designed to easily interface with microprocessors. The output data (12 bits, polarity and over-range) may be directly accessed under control of two byte enable inputs and a chip select input for a single parallel bus interface. A UART handshake mode is provided to allow the ICL7109 to work with industry-standard UARTs in providing serial data transmission. The RUN/HOLD input and STATUS output allow monitoring and control of conversion timing. The ICL7109 provides the user with the high accuracy, low noise, low drift versatility and economy of the dual-slope integrating A/D converter. Features like true differential input and reference, drift of less than 1µV/oC, maximum input bias current of 10pA, and typical power consumption of 20mW make the ICL7109 an attractive per-channel alternative to analog multiplexing for many data acquisition applications.
Part Number Information
PART NUMBER ICL7109MDL ICL7109ID L ICL7109IJL ICL7109CPL ICL7109MDL/883B ICL7109IP L TEMP. RANGE ( oC) -55 to 125 -25 to 85 -25 to 85 0 to 70 -55 to 125 -25 to 85 PACKAGE 40 Ld SBDIP 40 Ld SBDIP 40 Ld CERDIP 40 Ld PDIP 40 Ld SBDIP 40 Ld PDIP PKG. NO. D40.6 D40.6 F40.6 E40.6 D40.6 E40.6
Pinout
ICL7109 ( CERDIP, PDIP, SBDIP) TOP VIEW
G ND 1 40 V+ 39 REF IN 38 REF CAP37 REF CAP+ 36 REF IN+ 35 IN HI 34 IN LO 33 COMMON 32 INT 31 AZ 30 BUF 29 REF OUT 28 V27 SEND 26 RUN/HOLD 25 BUF OSC OUT 24 OSC SEL 23 OSC OUT 22 OSC IN 21 MODE
STATUS 2 POL OR B1 2 B1 1 B1 0 B9 B8 3 4 5 6 7 8 9
B7 10 B6 11 B5 12 B4 13 B3 14 B2 15 B1 16 TEST 17 LBEN 18 HBEN 19 CE/ LOAD 20
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved
File Number
3092.2
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ICL7109
Absolute Maximum Ratings
Positive Supply Voltage (GND to V+). . . . . . . . . . . . . . . . . . . . +6.0V Negative Supply Voltage (GND to V-) . . . . . . . . . . . . . . . . . . . . . -9V Analog Input Voltage (Either Input) (Note 1) . . . . . . . . . . . . V+ to VReference Input Voltage (Either Input) (Note 1) . . . . . . . . . . V+ to VDigital Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (V+) +0.3V Pins 2-27 (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.3V
Thermal Information
Thermal Resistance (Typical, Note 1) JA ( oC/W) JC (oC/W) SBDIP Package. . . . . . . . . . . . . . . . . . . . 60 20 CERD IP Package . . . . . . . . . . . . . . . . . . 55 18 PDIP Package . . . . . . . . . . . . . . . . . . . . . 50 N/A Maximum Junction Temperature (PDIP Package) . . . . . . . . . 150oC Maximum Junction Temperature (CERDIP Package). . . . . . . 175oC Maximum Storage Temperature Range . . . . . . . . . . - 65oC to 150oC Maximum Lead Temperature (Soldering 10s Max). . . . . . . . . 300oC
Operating Conditions
Temper ature Range M Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC I Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25oC to 85oC C Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to 75oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Analog Electrical Specifications V+ = +5V, V- = -5V, GND = 0V, TA = 25oC, fCLK = 3.58MHz,
Unless Otherwise Specified PARAMETER SY STE M PERFORMANCE Oscillator Output Current High, OOH Low, OOL Buffered Oscillator Output Current High, BOOH Low, BOOL Zero Input Reading Ratiometric Error Non-Linearity VOUT = 2.5V VOUT = 2.5V V IN = 0.0000V, VREF = 204.8mV VlN = VREF, VREF = 204.8mV (Note 7) Full Scale = 409.6mV to 2.048mV Maximum Deviation from Best Straight Line Fit, Over Full Operating Temperature Range (Notes 4 and 6) Full Scale = 409.6mV to 2.048V Difference in Reading for Equal Positive and Negative Inputs Near Full Scale (Notes 5 and 6), R1 = 0 Full-Scale = 200mV or Full Scale = 2V Maximum Deviation from Best Straight Line Fit (Note 4) - 0000 -3 -1 2 5 ±0000 ±0.2 +0000 0 +1 mA mA Counts Counts Counts VOUT = 2.5V VOUT = 2.5V 1 1.5 mA mA TEST CONDITIONS MIN TYP M AX UNIT
Rollover Error
-1
±0.2
+1
Counts
Linearity
(V -) +2.0 -
±0.2 50 15 1 20 100 2 0.2
±1 (V+) -2.0 10 100 250 100 1
Counts µV/V V µV pA pA pA nA µ V/oC
Common Mode Rejection Ratio, CMRR VCM = ±1V, VIN = 0V, Full Scale = 409.6mV Input Common Mode Range, VCMR Noise, eN Leakage Current Input, IILK ICL7109CPL ICL7109IDL ICL7109MDL Zero Reading Drift Input HI, Input LO, Common (Note 4) V IN = 0V, Full-Scale = 409.6mV (Peak-to-Peak Value Not Exceeded 95% of Time) VlN = 0V, All Devices at 25oC (Note 4) 0oC to 70oC (Note 4) -25oC to 85oC (Note 4) -55oC to 125oC V lN = 0V, R1 - 0 (Note 4)
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ICL7109
Analog Electrical Specifications V+ = +5V, V- = -5V, GND = 0V, TA = 25oC, fCLK = 3.58MHz,
Unless Otherwise Specified PA RAME TER Scale Factor Temperature Coefficient RE FERENC E VOLTAGE Ref Out Voltage, VREF Ref Out Temperature Coefficient POWER SUPPLY CHARACTERISTICS Supply Current V+ to GND, I+ Supply Current V+ to V-, ISUPP V IN = 0V, Crystal Osc 3.58MHz Test Circuit P ins 2 - 21, 25, 26, 27, 29; Open 700 700 1500 1500 µA µA Referred to V+, 25k Between V+ and REF OUT 25k Between V+ and REF OUT (Note 4) -2.4 -2.8 80 -3.2 V ppm/oC (Continued) MIN TYP 1 M AX 5 UNIT ppm/oC TEST CONDITIONS VIN = 408.9mV = > 77708 Reading Ext. Ref. 0ppm/oC (Note 4)
Digital Electrical Specifications V+ = +5V, V- = -5V, GND = 0V, TA = 25oC, Unless Otherwise Specified
PA RAMETER DIGITAL OUTPUTS Output High Voltage, VOH Output Low Voltage, V OL Output Leakage Current Control I/O Pullup Current Control I/O Loading DIGITAL INPUTS Input High Voltage, VIH Input Low Voltage, VIL Input Pull-Up Current Input Pull-Up Current Input Pull-Down Current TIMING CHARACTERISTICS MODE Input Pulse Width, tW (Note 4) 50 ns Pins 18 - 21, 26, 27 Referred to GND P ins 18 - 21, 26, 27 Referred to GND Pins 26, 27 V OUT = (V+) -3V Pins 17, 24 V OUT = (V+) -3V Pin 21 VOUT = GND +3V 3.0 5 25 5 1 V V µA µA µA IOUT = 100µA Pins 2 - 16, 18, 19, 20 IOUT = 1.6mA Pins 2 - 16, 18, 19, 20 P ins 3 - 16 High Impedance Pins 18, 19, 20 VOUT = V+ -3V MODE Input at GND (Note 4) HB EN Pin 19 LBEN Pin 18 (Note 4) 3.5 4.3 ±0.20 ±0.01 5 - ±0.40 ±1 50 V V µA µA pF TEST CONDITIONS MIN TYP M AX UNIT
NOTES : 1. Input voltages may exceed the supply voltages provided the input current is limited to ±100µA. 2. Due to the SCR structure inherent in the process used to fabricate these devices, connecting any digital inputs or outputs to voltages greater than V+ or less than GND may cause destructive device latchup. For this reason it is recommended that no inputs from sources other than the same power supply be applied to the ICL7109 before its power supply is established, and that in multiple supply systems the supply to the ICL7109 be activated first. 3. This limit refers to that of the package and will not be obtained during normal operation. 4. This parameter is not production tested, but is guaranteed by design. 5. Roll-over error for TA = -55oC to 125oC is ±10 counts (Max). 6. A full scale voltage of 2.048V is used because a full scale voltage of 4.096V exceeds the devices Common Mode Voltage Range. 7. For CERDIP package the Ratiometric error can be -4 (Min).
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