|
Details, datasheet, quote on part number:ICM7232CRIPL
| |
Datasheet text preview:
ICM7231, ICM7232
August 1997
Numeric/Alphanumeric Triplexed LCD Display Drivers
Description
The ICM7231 and ICM7232 family of integrated circuits are designed to generate the voltage levels and switching waveforms required to drive triplexed liquid-crystal displays. These chips also include input buffer and digit address decoding circuitry allowing six bits of input data to be decoded into 64 independent combinations of the output segments of the selected digit. The family is designed to interface to modern highperformance microprocessors and microcomputers and ease system requirements for ROM space and CPU time needed to service a display.
Features
· ICM7231 Drives 8 Digits of 7 Segments with Two Independent Annunciators Per Digit Address and Data Input in Parallel Format · ICM7232 Drives 10 Digits of 7 Segments with Two Independent Annunciators Per Digit Address and Data Input in Serial Format · All Signals Required to Drive Rows and Columns of Triplexed LCD Display are Provided · Display Voltage Independent of Power Supply · On-Chip Oscillator Provides All Display Timing · Total Power Consumption Typically 200µW, Maximum 500µW at 5V · Low-Power Shutdown Mode Retains Data With 5µW Typical Power Consumption at 5V, 1µW at 2V · Direct Interface to High-Speed Microprocessors
Ordering Information
PART NUMBER ICM7231BFIJL ICM7231BFIPL ICM7232BFIPL ICM7232CRIPL NOTE: All versions intended for triplexed LCD displays. TEMP. RANGE (oC) -25 to 85 -25 to 85 -25 to 85 -25 to 85 PACKAGE 40 Ld CERDIP 40 Ld PDIP 40 Ld PDIP 40 Ld PDIP NUMBER OF DIGITS 8 Digit 8 Digit 10 Digit 10 Digit INPUT FORMAT Parallel Parallel Serial Serial PKG. NO. F40.6 E40.6 E40.6 E40.6
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
File Number
3161.1
9-19
ICM7231, ICM7232 Pinouts
ICM7231BF (PDIP, CERDIP) TOP VIEW
CS VDISP BP1 BP2 BP3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 VDD 39 A2 38 A1 37 A0 36 VSS 35 BD3 34 BD2 33 BD1 32 BD0 31 AN2 30 AN1 29 f8, a8, an28 28 a8, g8, d8 27 b8, c8, an18 26 f7, e7, an27 25 a7, g7, d7 24 b7, c7, an17 23 f6, e6, an26 22 a6, g6, d6 21 b6, c6, an16 DATA CLOCK INPUT VDISP BP1 BP2 BP3 1 2 3 4 5 6 7 8 9
ICM7232AF, BF (PDIP, CERDIP) TOP VIEW
40 VDD 39 WRITE INPUT 38 DATA INPUT 37 DATA ACCEPTED OUTPUT 36 VSS 35 f10, e10, an210 34 a10, g10, d10 33 b10, c10, an110 32 f9, e9, an29 31 a9, g9, d9 30 b9, c9, an19 29 f8, a8, an28 28 a8, g8, d8 27 b8, c8, an18 26 f7, e7, an27 25 a7, g7, d7 24 b7, c7, an17 23 f6, e6, an26 22 a6, g6, d6 21 b6, c6, an16
b1, c1, an11 a1, g1, d1 f1, e1, an21 b2, c2, an12 a2, g2, d2 f2, e2, an22 b3, c3, an13 a3, g3, d3 f3, e3, an23 b4, c4, an14 a4, g4, d4 f4, e4, an24 b5, c5, an15 a5, g5, d5 f5, e5, an25
b1, c1, an11 a1, g1, d1 f1, e1, an21 b2, c2, an12
a2, g2, d2 10 f2, e2, an22 11 b3, c3, an13 12 a3, g3, d3 13 f3, e3, an23 14 b4, c4, an14 15 a4, g4, d4 16 f4, e4, an24 17 b5, c5, an15 18 a5, g5, d5 19 f5, e5, an25 20
ICM7232CR (PDIP) TOP VIEW
DATA CLOCK INPUT VDISP BP1 BP2 BP3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 VDD 39 WRITE INPUT 38 DATA INPUT 37 DATA ACCEPTED OUTPUT 36 VSS 35 b6, c6, an16 34 a6, g6, d6 33 f6, e6, an26 32 b7, c7, an17 31 a7, g7, d7 30 f7, e7, an27 29 b8, c8, an18 28 a8, g8, d8 27 f8, a8, an28 26 b9, c9, an19 25 a9, g9, d9 24 f9, e9, an29 23 b10, c10, an110 22 a10, g10, d10 21 f10, e10, an210
b1, c1, an11 a1, g1, d1 f1, e1, an21 b2, c2, an12 a2, g2, d2 f2, e2, an22 b3, c3, an13 a3, g3, d3 f3, e3, an23 b4, c4, an14 a4, g4, d4 f4, e4, an24 b5, c5, an15 a5, g5, d5 f5, e5, an25
9-20
ICM7231, ICM7232 Functional Block Diagrams
ICM7231
D8
D7
D6
D5
D4
D3
D2
D1
f1, e1, an21 a 1, g 1, d 1 b1, c1, an11
f2, e2, an22 a2, g2, d2 b2, c2, an12
SEGMENT LINE DRIVERS 3 WIDE OUTPUT LATCHES 9 WIDE
VDD ON CHIP DISPLAY VOLTAGE LEVEL GENERATOR
VH
VL VDISP
PIN 2 (INPUT) 9 9 9 9 9 9 9
9 COMMON LINE DRIVERS EN
BP1
BP2
DATA DECODER
DIGIT ADDRESS DECODER
BP3 ONE SHOT
DATA INPUT EN LATCHES
ADDRESS INPUT LATCHES
EN
DISPLAY TIMING GENERATOR
AN2 AN1 BD0
BD1 BD2
BD3 A0 A1 A2 CS
DATA INPUTS
ADDRESS INPUTS
NOTE: See Figure 13 for display segment connections.
9-21
|
|
