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Part: ISL5217EVAL1
Category:
Communication
-> Wireless
-> Commlink
Description: Quad Programmable up Converter
Company: Intersil Corporation
Datasheet: Download ISL5217EVAL1 datasheet File size : 416 kB
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Datasheet text preview:
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ISL5217
D a ta Sheet M arch 2003 FN6004.2
Quad Programmable Up Converter
The ISL5217 Quad Programmable UpConverter (QPUC) is a QASK/FM modulator/FDM upconverter designed for high dynamic range applications such as cellular basestations. The QPUC combines shaping and interpolation filters, a complex modulator, and timing and carrier NCOs into a single package. Each QPUC can create four FDM channels. Multiple QPUCs can be cascaded digitally to provide for up to 16 FDM channels in multi-channel applications. The ISL5217 supports both vector and FM modulation. In vector modulation mode, the QPUC accepts 16-bit I and Q samples to generate virtually any quadrature AM or PM modulation format. The QPUC also has two FM modulation modes. In the FM with pulse shaping mode, the 16-bit frequency samples are pulse shaped/bandlimited prior to FM modulation. No band limiting filter follows the FM modulator. This FM mode is useful for GMSK type modulation formats. In the FM with band limiting filter mode, the 16-bit frequency samples directly drive the FM modulator. The FM modulator output is filtered to limit the spectral occupancy. This FM mode is useful for analog FM or FSK modulation formats. The QPUC includes an NCO driven interpolation filter, which allows the input and output sample rate to have an integer and/or variable relationship. This re-sampling feature simplifies cascading modulators with sample rates that do not have harmonic or integer frequency relationships. The QPUC offers digital output spectral purity that exceeds 100dB at the maximum output sample rate of 104MSPS, for input sample rates as high as 6.5MSPS. A 16-bit microprocessor compatible interface is used to load configuration and baseband data. A programmable FIFO depth interrupt simplifies the interface to the I and Q input FIFOs.
Features
· Output Sample Rates Up to 104MSPS with Input Data Rates Up to 6.5MSPS · Processing Capable of >140dB SFDR Out of Band · Vector modulation for supporting IS-136, EDGE, IS95, TDSCDMA, CDMA-2000-1X/3X, W-CDMA, and UMTS · FM Modulation for Supporting AMPS, NMT, and GSM · Four Completely Independent Channels on Chip, Each With Programmable 256 Tap Shaping FIR, Half-Band, and High Order Interpolation Filters · 16-Bit parallel µProcessor Interface and Four Independent Serial Data Inputs · Two 20-bit I/O Buses and Two 20-bit Output Buses Allow Cascading Multiple Devices · 32-Bit Programmable Carrier NCO; 48-Bit Programmable Symbol Timing NCOs · Dynamic Gain Profiling and Output Routing Control
Applications
· Single or Multiple Channel Digital Software Radio Transmitters (Wide-Band or Narrow-Band) · Base Station Transmitter and Smart Antennas · Operates with HSP50216 in Software Radio Solutions · Compatible with the HI5960/ISL5961 or HI5828/ISL5929 D/A Converters
Ordering Information
PART NUMBER ISL52 17KI ISL5217EVAL1 TEMP RANGE (oC) -40 to 85 25 PACKAGE 196 Ld BGA Evaluation Kit PKG. NO V 196.15 x15
Block Diagram
INPUT I/Q SHAPING I/Q DATA FILTER/ FM MOD. I/Q HALF I/Q INTPL I/Q COMPLEX I/Q BAND MIXER FILTER SIN COS CARRIER NCO
GAIN CONTROL GAIN PROFILE
SDA SDB SDC SDD
I0 Q0 4 CH I1 SUM Q1 I2 Q2 I3 Q3
SAMPLE NCO
DELAY SUM
CAS IOUT(19:0) SUM
CAS SUM QOUT(19:0) QIN(19:0) IIN(19:0)
CHANNEL 0 CHANNEL 1 CHANNEL 2 CHANNEL 3
P A {CNTRL}
1 2 3 4
PARALLEL HOST INTERFACE
CONFIGURATION AND CONTROL BUS
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003. All Rights Reserved. CommLinkTM is a trademark of Intersil Americas Inc. All other trademarks mentioned are the property of their respective owners.
Functional Block Diagram
ISL5217
SCLKA FSRA INTERFACE I IN Q IN MUX INTERPOLATION FILTER SDA SDB SDC SDD MUX SERIAL FM MOD. I FM 18 / Q FM 18 / I SF 20 / SHAPING FILTER LIMITER MUX
1-7 DEEP FIFO
20 / 20 /
MUX
HALF BAND
21 / COMPLEX 21 MIXER /
GAIN CONTROL
GAIN PROFILE
I Q 4 INPUT SUMMER 1
I IN Q IN SER._PAR.
/ 16 I FIFO / / Q FIFO 16 /
COS
CHANNEL UP INTERFACE AND TIMING
OUTPUT_EN CARRIER PHASE CARRIER FREQUENCY DUALQUADMODE (CH0 AND CH2 ONLY) ROUTEBUS_UPDATE
CARRIER NCO CHANNEL 0 I Q CH_EN I Q CH_EN I Q CH_EN
SIN
COARSE PHASE
FINE PHASE
ROUTING CONTROL
PROGRAMMABLE DELAY
TX_ENABLE UPDATE CH_SELECT
2
CLK A P TXENA TXENB TXENC TXEND UPDA UPDB UPDC UPDD WR RD CS RESET RDMODE OUTEN TRITST OFFBIN TMS TDI TCK TRST
BYPASS
CH_ENABLE
MOD. TYPE FID SR SAMPLE INTPL PHASES NCO PHASE OFFSET GAIN GAIN PROFILE LENGTH
ISL5217
CHANNEL 1
4 INPUT SUMMER 2 4 INPUT SUMMER 3 4 INPUT SUMMER 4
SCLKB FSRB SCLKC FSRC SCLKD FSRD ISTRB
CHANNEL 2
ISTROBEUPDATE RESET CASCADE_DELAY ROUTEBUS CASCADE_IN_ENABLE OUTPUTMODE OUTPUTMODE2X I_STROBE_EN ISTROBEPOLARITY TRITST_ENABLE_BUS
CHANNEL 3
DEVICE UPROCESSOR INTERFACE
OUTPUT CONTROL
IOUT QOUT IIN QIN
SYNCO
JTAG
TDO
ISL5217 Pinout
196 LdBGA
TOP VIEW
1 2 3 4 5 6 7 8 9 10 11 12 13 14
A IOUT14 IOUT13 IOUT12 IOUT10 B IOUT16 IOUT15 IOUT11 VCCIO IOUT9 C IOUT18 D IOUT19 E VCCC QOUT17 QOUT18 RESET QOUT14 QOUT11 QOUT8 QOUT7 QOUT5 QOUT2 F ISTRB G CLK H TCK J IIN19 K GND L IIN18 M IIN1 6 N IIN14 P IIN1 3 IIN12 IIN10 IIN8 VCCC IIN6 IIN4 IIN2 IIN0 GND SDA SDC TXENB SCLKA IIN15 IIN9 GND IIN7 VCCC IIN3 IIN1 GND QIN0 VCCIO TXENA TXENC SCLKB IIN17 IIN11 GND QIN10 IIN5 GND QIN4 QIN1 SDB SDD UPDB TXEND SCLKC VCCIO QIN13 VCCIO QIN11 QIN8 QIN6 VCCC QIN2 RDMODE VCCIO GND GND SCLKD QIN15 QIN14 QIN12 OFFBIN QIN9 QIN7 QIN5 QIN3 FSRA UPDA UPDD UPDC VCCC GND QIN16 TDI TDO SYNCO FSRC FSRB VCCC FSRD QIN17 QIN19 GND V C C C O U TE N 0 A1 VCCC A3 A4 A2 VCCC QOUT19 TRITST OUTEN1 A6 P0 GND P1 A5 P2 P5 P3 GND GND GND VCCIO QOUT13 QOUT10 VCCC Q O U T6 Q O U T4 Q O U T1 VCCC IOUT17 QOUT16 QOUT15 QOUT12 QOUT9 IOUT7 GND QOUT3 QOUT0 GND P14 P8 P6 G ND IOUT5 IOUT3 VCCIO IOUT1 GND P13 P10 P9 GND IOUT8 IOUT6 IOUT4 IOUT2 VCCIO I OUT0 P15 P12 P11
P7
VCCC
P4
QIN18
TM S
TRST
A0
CS
GND
WR
RD
POWER PIN GROUND PIN
SIGNAL PIN THERMAL BALL NC (NO CONNECTION)
NOTE: Thermal balls should be connected to the ground plane.
3
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