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Details, datasheet, quote on part number:ISL6551AB-T
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ISL6551
D a ta Sheet A u g us t 2003 FN9066.2
ZVS Full Bridge PWM Controller
The ISL6551 is a zero voltage switching (ZVS) full-bridge PWM controller designed for isolated power systems. This part implements a unique control algorithm for fixedfrequency ZVS current mode control, yielding high efficiency with low EMI. The two lower drivers are PWM-controlled on the trailing edge and employ resonant delay while the two upper drivers are driven at a fixed 50% duty cycle. This IC integrates many features in both 6x6 mm2 QFN and 28-lead SOIC packages to yield a complete and sophisticated power supply solution. Control features include programmable soft start for controlled start up, programmable resonant delay for zero voltage switching, programmable leading edge blanking to prevent false triggering of the PWM comparator due to the leading edge spike of the current ramp, adjustable ramp for slope compensation, drive signals for implementing synchronous rectification in high output current, ultra high efficiency applications, and current share support for paralleling up to 10 units, which helps achieve higher reliability and availability as well as better thermal management. Protective features include adjustable cycle-by-cycle peak current limiting for overcurrent protection, fast short-circuit protection (in hiccup mode), a latching shutdown input to turn off the IC completely on output over-voltage conditions or other extreme and undesirable faults, a non-latching enable input to accept an enable command when monitoring the input voltage and thermal condition of a converter, and VDD under voltage lockout with hysteresis. Additionally, the ISL6551 includes high current high-side and low-side totem-pole drivers to avoid additional external drivers for moderate gate capacitance (up to 1.6nF at 1MHz) applications, an uncommitted high bandwidth (10MHz) error amplifier for feedback loop compensation, a precision bandgap reference with ±1.5% (ISL6551AB) or ±1% (ISL6551IB) tolerance over recommended operating conditions, and an ±5% "in regulation" monitor. In addition to the ISL6551, other external elements such as transformers, pulse transformers, capacitors, inductors and Schottky or synchronous rectifiers are required for a complete power supply solution. A detailed 200W telecom power supply reference design using the ISL6551 with companion Intersil ICs, Supervisor And Monitor ISL6550 and Half-bridge Driver HIP2100, is presented in Application Note AN1002. In addition, the ISL6551 can also be designed in push-pull converters using all of the features except the two upper drivers and adjustable resonant delay features.
Features
· High Speed PWM (up to 1MHz) for ZVS Full Bridge Control · Current Mode Control Compatible · High Current High-side and Low-side Totem-pole Drivers · Adjustable Resonant Delay for ZVS · 10MHz Error Amplifier Bandwidth · Programmable Soft Start · Precision Bandgap Reference · Latching Shutdown Input · Non-latching Enable Input · Adjustable Leading Edge Blanking · Adjustable Dead Time Control · Adjustable Ramp for Slope Compensation · Fast Short-circuit Protection (Hiccup Mode) · Adjustable Cycle-by-Cycle Peak Current Limiting · Drive Signals to Implement Synchronous Rectification · VDD Under-voltage Lockout · Current Share Support · ±5% "In Regulation" Indication · QFN Package: - Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat No Leads - Package Outline - Near Chip Scale Package footprint, which improves PCB efficiency and has a thinner profile
Applications
· Full-Bridge and Push-Pull Converters · Power Supplies for Off-line and Telecom/Datacom · Power Supplies for High End Microprocessors and Servers
Ordering Information
PART NUMBER ISL65 51IB ISL65 51IB-T ISL65 51IR ISL65 51IR-T ISL65 51AB ISL6551AB-T ISL6551EVAL1 TEMP RANGE (oC) 0 to 85 0 to 85 0 to 85 0 to 85 -40 to 105 -40 to 105 P ACK AGE 28 Lead SOIC Tape & Reel 28 Lead 6x6 QFN Tape & Reel 28 Lead SOIC Tape & Reel PKG. DWG. # M28.3 M28.3 L28.6x6 L28.6x6 M28.3 M28.3
Evaluation Platform (ISL6551IR only)
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
ISL6551 Pinouts
28 PIN WIDE BODY (SOIC) TOP VIEW
RD CT VSS CT RD R_RESDLY R_RA ISENSE PKILIM BGREF R_LEB CS_COMP CSS 1 2 3 4 5 6 7 8 9 10 11 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD VDDP1 VDDP2 PGND UPPER1 UPPER2 LOWER1 LOWER2 SYNC1 SYNC2 ON/OFF DCOK LATSD CSS SHARE EAI EANI EAO LATSD DCOK SHARE 8 9 10 11 12 13 14 R_RESDLY R_RA ISENSE PKILIM BGREF R_LEB CS_COMP 1 2 3 4 5 6 7
28 PIN (QFN) TOP VIEW
VDDP1 VDDP2 23 PGND 22 21 20 19 18 17 16 15 UPPER1 UPPER2 LOWER1 LOWER2 SYNC1 SYNC2 ON/OFF VDD 25 VSS 26
28
27
24
EANI 12 EAI 13 EAO 14
Functional Pin Description
PACKAGE PIN # SOIC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19, 20 21, 22 23, 24 25 26, 27 28 QFN 26 27 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16, 17 18, 19 20, 21 22 23, 24 25 PIN SYMBOL VSS CT RD R_RESDLY R_RA ISENSE PKILIM BGREF R _LEB CS_COMP CSS EANI EAI EAO SHARE LATSD DC OK ON/OFF SYNC2, SYNC1 LOWER2, LOWER1 UPPER2, UPPER1 PGND VDDP2, VDDP1 VDD FUNCTION Reference ground. All control circuits are referenced to this pin. Set the oscillator frequency, up to 1MHz. Adjust the clock dead time from 50ns to 1000ns. Program the resonant delay from 50ns to 500ns. Adjust the ramp for slope compensation (from 50mV to 250mV). The pin receives the current information via a current sense transformer or a power resistor. Set the over current limit with the bandgap reference as the trip threshold. Precision bandgap reference, 1.263V ±2% overall recommended operating conditions. Program the leading edge blanking from 50ns to 300ns. Set a low current sharing loop bandwidth with a capacitor. Program the rise time and the clamping voltage with a capacitor and a resistor, respectively. Non-inverting input of Error Amp. It is clamped by the voltage at the CSS pin (Vclamp). Inverting input of Error Amp. It receives the feedback voltage. Output of Error Amp. It is clamped by the voltage at the CSS pin (Vclamp). This pin is the SHARE BUS connecting with other unit(s) for current share operation. The IC is latched off with a voltage greater than 3V at this pin and is reset by recycling VDD. Power Good indication with a ±5% window. This is an Enable pin that controls the states of all drive signals and the soft start. These are the gate control signals for the output synchronous rectifiers. Both lower drivers are PWM-controlled on the trailing edge. Both upper drivers are driven at a fixed 50% duty cycle. Power Ground. High current return paths for both the upper and the lower drivers. Power is delivered to both the upper and the lower drivers through these pins. Power is delivered to all control circuits including SYNC1 & SYNC2 via this pin.
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ISL6551 Functional Block Diagram
18 ON/OFF 1 6 LATSD
28 VDD
BAND GAP REFERENCE
UVLO
SHUTDOWN SHUTDOWN L A TC H LAT CH SOFT SOFT START START
BGREF
8
PKILIM 7
SHUTDOWN
11 CSS
27 VDDP1
UPPER1 DRIVER R_LEB 9 R_RESDLY 4 RESODLY LEB ISENSE 6 R_RA 5 RAMP ADJUST UPPER2 DRIVER
24 UPPER1
23 UPPER2
CT 2 RD 3
26 VDDP2 CL OCK GENERATOR PWM LOGIC LO WER1 DRIVER 22 LOWER1
EAO 14
ERROR AMP (See Fig. 4)
LO WER2 DRIVER EAI 13 EANI 12 DC OK CURRENT SHARE
21 LOWER2
CIRCUITS REFERENCED TO VSS
17 DCOK
10 CS_COMP
1 5 SHARE
19 SYNC2
20 SYNC1
25 PGND
1 VSS
CIRCUITS REFERENCED TO PGND
EXTERNAL SINGLE POINT CONNECTION REQUIRED
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