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Details, datasheet, quote on part number:LM555
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| Part: | LM555 |
| Category: | Timing Circuits => Oscillators |
| Description: | Timers For Timing Delays And Oscillator Application in Commercial, Industrial And Military Equipment |
| Company: | Intersil Corporation |
| Datasheet: | Download LM555 datasheet File size : 66 kB |
| Request For quote: | Find where to buy LM555
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Datasheet text preview:
Semiconductor
PO
UCT UCT D ROD TE P TE PRO E SOL STITU OB UB 5 LE S ICM755 SSIB
CA555, CA555C, LM555C
December 1999 File Number 834.6
Timers for Timing Delays and Oscillator Applications in Commercial, Industrial and Military Equipment
[ /Title The CA555 and CA555C are highly stable timers for use in (CA55 precision timing and oscillator applications. As timers, these 5, monolithic integrated circuits are capable of producing CA555 accurate time delays for periods ranging from microseconds through hours. These devices are also useful for astable C, LM555 oscillator operation and can maintain an accurately controlled free running frequency and duty cycle with only C) two external resistors and one capacitor. /SubThe circuits of the CA555 and CA555C may be triggered by ject the falling edge of the waveform signal, and the output of (Tim- these circuits can source or sink up to a 200mA current or ers for drive TTL circuits. Timing These types are direct replacements for industry types in Delays packages with similar terminal arrangements e.g. SE555 and and NE555, MC1555 and MC1455, respectively. The CA555 Oscilla- type circuits are intended for applications requiring premium electrical performance. The CA555C type circuits are tor Appli- intended for applications requiring less stringent electrical cations characteristics. in Part Number Information ComPART NUMBER TEMP. PKG. mer(BRAND) RANGE (oC) PACKAGE NO. cial, CA0555E -55 to 125 8 Ld PDIP E8.3 IndusCA0555CE 0 to 70 8 Ld PDIP E8.3 trial LM555CN 0 to 70 8 Ld PDIP E8.3 and MiliPinout tary CA555, CA555C, LM555C, (PDIP) EquipTOP VIEW ment) 8 V+ GND 1 /Author 7 DISCHARGE TRIGGER 2 () OUTPUT 3 6 THRESHOLD /Key5 CONTROL RESET 4 words VOLTAGE (Harris Semiconductor, single, timer,
Features
· Accurate Timing From Microseconds Through Hours · Astable and Monostable Operation · Adjustable Duty Cycle · Output Capable of Sourcing or Sinking up to 200mA · Output Capable of Driving TTL Devices · Normally ON and OFF Outputs · High Temperature Stability . . . . . . . . . . . . . . . . 0.005%/oC · Directly Interchangeable with SE555, NE555, MC1555, and MC1455
Applications
· Precision Timing · Sequential Timing · Time Delay Generation · Pulse Generation · Pulse Detector · Pulse Width and Position Modulation
Functional Block Diagram
V+ TRIGGER CONTROL 8 VOLTAGE 5 2
THRESHOLD
TRIGGER COMPAR 6 OUTPUT THRESHOLD COMPAR FLIP-FLOP
3
7
RESET
4
1 GND
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. Copyright © Harris Corporation 1999
DISCHARGE OUTPUT
CA555, CA555C, LM555C
Absolute Maximum Ratings
DC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18V
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) JC (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . 100 N/A Maximum Junction Temperature (Plastic Package) . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
Operating Conditions
Temperature Range CA555 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC CA555C, LM555C . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER DC Supply Voltage DC Supply Current (Low State) (Note 2) Threshold Voltage Trigger Voltage
TA = 25oC, V+ = 5V to 15V Unless Otherwise Specified CA555 SYMBOL V+ I+ V+ = 5V, RL = V+ = 15V, RL = VTH V+ = 5V V+ = 15V TEST CONDITIONS MIN 4.5 1.45 4.8 ITH 0.4 V+ = 5V V+ = 15V 2.9 9.6 3.0 13.0 tR tF TYP 3 10 (2/3)V+ 1.67 5 0.5 0.1 0.7 0.1 3.33 10 0.1 0.1 0.4 2.0 2.5 3.3 13.3 12.5 0.5 30 0.05 100 100 MAX 18 5 12 1.9 5.2 0.25 1.0 3.8 10.4 0.25 0.15 0.5 2.2 2 100 0.2 CA555C, LM555C MIN 4.5 0.4 2.6 9 2.75 12.75 TYP 3 10 (2/3)V+ 1.67 5 0.5 0.1 0.7 0.1 3.33 10 0.25 0.1 0.4 2.0 2.5 3.3 13.3 12.5 1 50 0.1 100 100 MAX 16 6 15 0.25 1.0 4 11 0.35 0.25 0.75 2.5 UNITS V mA mA V V V µA µA V mA V V V V V V V V V V V % ppm/oC %/V ns ns
Trigger Current Threshold Current (Note 3) Reset Voltage Reset Current Control Voltage Level
Output Voltage Low State
VOL
V+ = 5V, ISINK = 5mA ISINK = 8mA V+ = 15V, ISINK = 10mA ISINK = 50mA ISINK = 100mA ISINK = 200mA
Output Voltage High State
VOH
V+ = 5V, ISOURCE = 100mA
V+ = 15V, ISOURCE = 100mA
ISOURCE = 200mA Timing Error (Monostable) Frequency Drift with Temperature Drift with Supply Voltage Output Rise Time Output Fall Time NOTES: R1, R2 = 1k to 100k, C = 0.1µF Tested at V+ = 5V, V+ = 15V
2. When the output is in a high state, the DC supply current is typically 1mA less than the low state value. 3. The threshold current will determine the sum of the values of R1 and R2 to be used in Figure 4 (astable operation); the maximum total R1 + R2 = 20M.
2
CA555, CA555C, LM555C Schematic Diagram
V+ 8 4.7K 830 D1 4.7K D2 Q10 Q3 Q4 1K 5K 6.8K THRESHOLD COMPARATOR TRIGGER COMPARATOR FLIP-FLOP OUTPUT
Q16 Q19 Q20 3.9K OUTPUT 3
THRESHOLD 6 Q1 Q2 Q5 5K 10K CONTROL VOLTAGE 5 2 TRIGGER RESET 4 RESET 7 DISCHARGE 1 VQ6 DISCHARGE 100 Q8 100K Q9 Q11 Q12 Q13 5K Q14 Q7 4.7K
7K
D3
D4
Q18 220 Q17 Q15 4.7K Q21
NOTE: Resistance values are in ohms.
Typical Applications
Reset Timer (Monostable Operation)
Figure 1 shows the CA555 connected as a reset timer. In this mode of operation capacitor CT is initially held discharged by a transistor on the integrated circuit. Upon closing the "start" switch, or applying a negative trigger pulse to terminal 2, the integral timer flip-flop is "set" and releases the short circuit across CT which drives the output voltage "high" (relay energized). The action allows the voltage across the capacitor to increase exponentially with the constant t = R1CT. When the voltage across the capacitor equals 2/3 V+, the comparator resets the flip-flop which in turn discharges the capacitor rapidly and drives the output to its low state. Since the charge rate and threshold level of the comparator are both directly proportional to V+, the timing interval is relatively independent of supply voltage variations. Typically, the timing varies only 0.05% for a 1V change in V+. Applying a negative pulse simultaneously to the reset terminal (4) and the trigger terminal (2) during the timing cycle discharges CT and causes the timing cycle to restart. Momentarily closing only the reset switch during the timing inter val discharges CT, but the timing cycle does not restart.
R1 7 CA555 6 1 2 CT 4.7K S1 START 5 10K RELAY COIL RESET 680 4 8 EO 3 1N4001 V+ 5V
0.01µF
680
NOTE: All resistance values are in ohms. FIGURE 1. RESET TIMER (MONOSTABLE OPERATION)
3
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