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Part: IN74ALS373DW
Category:
Logic
Description: Octal D-type Latch (3-State) 20
Company: IK Semiconductor
Datasheet: Download IN74ALS373DW datasheet File size : 288 kB
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TECHNICAL DATA
IN74ALS373
Octal D-Type 3-State Transparent Latch
These 8-bit registers feature totem-pole 3-State outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance state and increased high-logic-level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pull-up components. They are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight latches of the ALS373 are transparent D-type latches. While the Latch Enable is high the Q outputs will follow the data(D) inputs. When the enable is taken low the output will be latched at the level of the data that was set up. A buffered output control input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state the outputs neither load nor drive the bus lines significanty. The output control does not affect the internal operation of the latches. That is, the old data can be retained or new data can be entered even while the outputs are off. · Switching specifications at 50 pF · Switching specifications guaranteed over full temperature and VCC range · Functionally and pin for pin compatible with LS TTL counterpart · Improved AC performance over LS373 at approximately half the power · TRI-STATE buffer-type outputs drive bus lines directly
ORDERING INFORMATION IN74ALS373N Plastic IN74ALS373DW SOIC TA = -10° to 70° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
Inputs Output Enable L L L H PIN 20=VCC PIN 10 = GND Latch Enable H H L X D H L X X Output Q H L No Change Z
X = Don't Care Z = High Impedance
1
IN74ALS373
MAXIMUM RATINGS*
Symbol VCC VIN V OUT Tstg
*
Parameter Supply Voltage Input Voltage Output Voltage (Referenced to GND) Storage Temperature Range
Value 7.0 7 .0 5 .5 -65 to +150
Unit V V V °C
Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VIH VIL I OH I OL TA Supply Voltage High Level Input Voltage Low Level Input Voltage High Level Output Current Low Level Output Current Ambient Temperature Range -10 Parameter Min 4.5 2 .0 0 .8 -2.6 24 +70 M ax 5.5 Unit V V V mA mA °C
DC ELECTRICAL CHARACTERISTICS over full operating conditions
Guaranteed Limit Symbol VIK V OH V OL I OZH I OZL IIH IIL IO ICC Parameter Input Clamp Voltage High Level Output Voltage Low Level Output Voltage Output Off Current HIGH Output Off Current LOW High Level Input Current Low Level Input Current Output Short Circuit Current Supply Current Test Conditions VCC = min, IIN = -18 mA VCC = min, IOH = -0.4 mA VCC = min, IOH = -2.6 mA VCC = min, IOL = 12 mA VCC = min, IOL = 24 mA VCC = max, VOUT = 2.7 V VCC = max, VOUT = 0.4 V VCC = max, VIN = 2.7 V VCC = max, VIN = 7.0 V VCC = max, VIN = 0.4 V VCC = max, VO = 2.25 V VCC = max Outputs Low Outputs High 3-State (High Z) -30 2.5 2.4 0.4 0.5 20 -20 20 0 .1 -0.1 -112 16 25 27 µA µA µA mA mA mA mA V Min M ax -1.5 Unit V V
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IN74ALS373
AC ELECTRICAL CHARACTERISTICS over full operating conditions (VCC = 5.0 V±10%, CL = 50 pF, RL1 = RL2 = 500 , Input tr = tf = 2.0 ns)
Guaranteed Limit Symbol tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tw tsu th Parameter Propagation Delay Time, Data to Any Q Propagation Delay Time, Data to Any Q Propagation Delay Time, Latch Enable to Any Q Propagation Delay Time, Latch Enable to Any Q Propagation Delay Time, Output Enable to Any Q Propagation Delay Time, Output Enable to Any Q Propagation Delay Time, Output Enable to Any Q Propagation Delay Time, Output Enable to Any Q Enable Width Setup Time Hold Time 10 10 7 Min M ax 12 16 22 23 20 18 40 30 Unit ns ns ns ns ns ns ns ns ns ns ns
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
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