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Details, datasheet, quote on part number:IS41C4100-60JI
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Datasheet text preview:
IS41C4100 IS41LV4100
1Meg x 4 (4-MBIT) DYNAMIC RAM WITH EDO PAGE MODE
FEATURES
· TTL compatible inputs and outputs · Refresh Interval: 1024 cycles/16 ms · Refresh Mode : RAS-Only, CAS-before-RAS (CBR), and Hidden · JEDEC standard pinout · Single power supply 5V ± 10% (IS41C4100) 3.3V ± 10% (IS41LV4100) · Industrail Temperature Range -40oC to 85oC
ISSI
DESCRIPTION
®
PRELIMINARY INFORMATION SEPTEMBER 2001
The ISSI IS41C4100 and IS41LV4100 are 1,048,576 x 4-bit high-performance CMOS Dynamic Random Access Memory. Both products offer accelerated cycle access EDO Page Mode. EDO Page Mode allows 512 random accesses within a single row with access cycle time as short as 10ns per 4-bit word. These features make the IS41C4100 and IS41LV4100 ideally suited for high band-width graphics, digital signal processing, high-performance computing systems, and peripheral applications. The IS41C4100 and IS41LV4100 are available in a 20-pin, 300-mil SOJ package.
KEY TIMING PARAMETERS
Parameter Max. RAS Access Time (tRAC) Max. CAS Access Time (tCAC) Max. Column Address Access Time (tAA) Min. Fast Page Mode Cycle Time (tPC) Min. Read/Write Cycle Time (tRC) -35 35 10 18 12 60 -60 60 15 30 25 110 Unit ns ns ns ns ns
PIN CONFIGURATION 20-Pin SOJ
I/O0 I/O1 WE RAS A9
1 2 3 4 5
20 19 18 17 16
GND I/O3 I/O2 CAS OE
PIN DESCRIPTIONS
A0-A9 I/O0-I/O3 WE OE RAS CAS VCC GND NC Address Inputs Data Inputs/Outputs Write Enable Output Enable Row Address Strobe Column Address Strobe Power Ground No Connection
A0 A1 A2 A3 Vcc
6 7 8 9 10
15 14 13 12 11
A8 A7 A6 A5 A4
This document contains PRELIMINARY INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. -- 1-800-379-4774
PRELIMINARY INFORMATION 09/10/01 Rev. 00A
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IS41C4100 IS41LV4100
FUNCTIONAL BLOCK DIAGRAM
OE WE CAS CLOCK GENERATOR WE CONTROL LOGICS OE CONTROL LOGIC OE RAS
ISSI
®
CAS
CAS
WE
RAS
RAS CLOCK GENERATOR
DATA I/O BUS
COLUMN DECODERS SENSE AMPLIFIERS
REFRESH COUNTER
DATA I/O BUFFERS
I/O0-I/O3
ROW DECODER
ADDRESS BUFFERS A0-A9
MEMORY ARRAY 1,048,576 x 4
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Integrated Silicon Solution, Inc. -- 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A 09/10/01
IS41C4100 IS41LV4100
TRUTH TABLE
Function Standby Read: Word Read: Lower Byte Read: Upper Byte Write: Word (Early Write) Write: Lower Byte (Early Write) Write: Upper Byte (Early Write) R e a d - W r i t e (1,2) EDO Page-Mode Read(2) DOUT RAS H L L L L L L L 1st Cycle: 2nd Cycle: Any Cycle: EDO Page-Mode Write(1) EDO Page-Mode DOUT, DIN R e a d - W r i t e (1,2) Hidden Refresh DOUT DOUT RAS-Only Refresh CBR Refresh(3) L HL H L X X X X ROW/NA X
2)
ISSI
CAS H L L H L L H L L L L L L L L LHL LHL WE X H H H L L L HL HL HL LH HL HL HL HL L L O E Address tR/tC X L L L X X X LH H H H L L HL HL H L X ROW/COL ROW/COL ROW/COL ROW/COL ROW/COL ROW/COL ROW/COL L L L X X LH LH L X I/O High-Z DOUT Lower Byte, DOUT Upper Byte, High-Z Lower Byte, High-Z Upper Byte, DOUT DIN Lower Byte, DIN Upper Byte, High-Z Lower Byte, High-Z Upper Byte, DIN DOUT, DIN ROW/COL NA/COL DOUT NA/NA DOUT ROW/COL, DIN NA/COL DIN ROW/COL N A / C O L DOUT, DIN ROW/COL ROW/COL High-Z High-Z
®
1st Cycle: 2nd Cycle: 1st Cycle: 2nd Cycle: Read Write
Notes: 1. These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active). 2. These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active). 3. At least one of the two CAS signals must be active (LCAS or UCAS).
Integrated Silicon Solution, Inc. -- 1-800-379-4774
PRELIMINARY INFORMATION 09/10/01 Rev. 00A
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