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Part: IS41LV16105-50KE
Category:
Memory
-> DRAM
-> EDO/FPM DRAM
Description: 3.3V 1M X 16(16-MBIT) Dynamic RAM With Fast Page Mode
Company: Integrated Silicon Solution
Datasheet: Download IS41LV16105-50KE datasheet File size : 148 kB
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Datasheet text preview:
IS41C16105 IS41LV16105
1M x 16 (16-MBIT) DYNAMIC RAM WITH FAST PAGE MODE
FEATURES
· TTL compatible inputs and outputs; tristate I/O · Refresh Interval: -- 1,024 cycles/16 ms · Refresh Mode: -- RAS-Only, CAS-before-RAS (CBR), and Hidden · JEDEC standard pinout · Single power supply: -- 5V ± 10% (IS41C16105) -- 3.3V ± 10% (IS41LV16105) · Byte Write and Byte Read operation via two CAS · Extended Temperature Range -30oC to 85oC · Industrail Temperature Range -40oC to 85oC
ISSI
DESCRIPTION
®
FEBRUARY 2000
The ISSI IS41C16105 and IS41LV16105 are 1,048,576 x 16-bit high-performance CMOS Dynamic Random Access Memories. Fast Page Mode allows 1,024 random accesses within a single row with access cycle time as short as 20 ns per 16-bit word. The Byte Write control, of upper and lower byte, makes the IS41C16105 ideal for use in 16-, 32-bit wide data bus systems. These features make the IS41C16105 and IS41LV16105 ideally suited for high-bandwidth graphics, digital signal processing, highperformance computing systems, and peripheral applications. The IS41C16105 and IS41LV16105 are packaged in a 42-pin 400-mil SOJ and 400-mil 44- (50-) pin TSOP (Type II).
KEY TIMING PARAMETERS
Parameter Max. RAS Access Time (tRAC) Max. CAS Access Time (tCAC) Max. Column Address Access Time (tAA) Min. Fast Page Mode Cycle Time (tPC) Min. Read/Write Cycle Time (tRC) -50 50 13 25 20 84 -60 60 15 30 25 104 Unit ns ns ns ns ns
PIN CONFIGURATIONS
44(50)-Pin TSOP (Type II) 42-Pin SOJ
VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC NC NC WE RAS NC NC A0 A1 A2 A3 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
GND I/O15 I/O14 I/O13 I/O12 GND I/O11 I/O10 I/O9 I/O8 NC NC LCAS UCAS OE A9 A8 A7 A6 A5 A4 GND
VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC NC WE RAS NC NC A0 A1 A2 A3 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
GND I/O15 I/O14 I/O13 I/O12 GND I/O11 I/O10 I/O9 I/O8 NC LCAS UCAS OE A9 A8 A7 A6 A5 A4 GND
PIN DESCRIPTIONS
A0-A9 I/O0-15 WE OE RAS UCAS LCAS Vcc GND NC Address Inputs Data Inputs/Outputs Write Enable Output Enable Row Address Strobe Upper Column Address Strobe Lower Column Address Strobe Power Ground No Connection
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. A 03/03/00
1
IS41C16105 IS41LV16105
FUNCTIONAL BLOCK DIAGRAM
ISSI
®
OE WE LCAS UCAS CAS CLOCK GENERATOR WE CONTROL LOGICS OE CONTROL LOGIC OE
CAS
WE
RAS
RAS CLOCK GENERATOR
DATA I/O BUS
REFRESH COUNTER
DATA I/O BUFFERS
ROW DECODER
RAS
COLUMN DECODERS SENSE AMPLIFIERS
I/O0-I/O15
MEMORY ARRAY 1,048,576 x 16
ADDRESS BUFFERS A0-A9
2
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. A 03/03/00
IS41C16105 IS41LV16105
TRUTH TABLE
Function Standby Read: Word Read: Lower Byte Read: Upper Byte Write: Word (Early Write) Write: Lower Byte (Early Write) Write: Upper Byte (Early Write) Read-Write(1,2) Hidden Refresh RAS-Only Refresh CBR Refresh
(4)
ISSI
RAS H L L L L L L L Read(2) W r i t e( 1 , 3 ) LHL LHL L HL LCAS H L L H L L H L L L H L UCAS H L H L L H L L L L H L WE X H H H L L L HL H L X X OE X L L L X X X LH L X X X Address tR/tC X ROW/COL ROW/COL ROW/COL ROW/COL ROW/COL ROW/COL ROW/COL ROW/COL ROW/COL ROW/NA X I/O High-Z DOUT Lower Byte, DOUT Upper Byte, High-Z Lower Byte, High-Z Upper Byte, DOUT DI N Lower Byte, DIN Upper Byte, High-Z Lower Byte, High-Z Upper Byte, DIN DOUT, DIN DOUT DOUT High-Z High-Z
®
Notes: 1. These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active). 2. These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active). 3. EARLY WRITE only. 4. At least one of the two CAS signals must be active (LCAS or UCAS).
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. A 03/03/00
3
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