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Details, datasheet, quote on part number:IS42S16400A-10T
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Datasheet text preview:
IS42S16400A
1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
FEATURES
· Clock frequency:166, 133, 100 MHz · Fully synchronous; all signals referenced to a positive clock edge · Internal bank for hiding row access/precharge · Single 3.3V power supply · LVTTL interface · Programmable burst length (1, 2, 4, 8, full page) · Programmable burst sequence: Sequential/Interleave · Self refresh modes · 4096 refresh cycles every 64 ms · Random column address every clock cycle · Programmable CAS latency (2, 3 clocks) · Burst read/write and burst read/single write operations capability · Burst termination by burst stop and precharge command · Byte controlled by LDQM and UDQM · Industrial temperature availability (133MHz, 100MHz) · Package: 400-mil 54-pin TSOP II, a lead-free package is available.
ISSI
April 2003
®
OVERVIEW ISSI's 64Mb Synchronous DRAM IS42S16400A is organized
a s 1,048,576 bits x 16-bit x 4-bank for improved performance. The synchronous DRAMs achieve high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input.
PIN CONFIGURATIONS
54-Pin TSOP (Type II)
VCC I/O0 VCCQ I/O1 I/O2 GNDQ I/O3 I/O4 VCCQ I/O5 I/O6 GNDQ I/O7 VCC LDQM WE CAS RAS CS BA0 BA1 A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 GND I/O15 GNDQ I/O14 I/O13 VCCQ I/O12 I/O11 GNDQ I/O10 I/O9 VCCQ I/O8 GND NC UDQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 GND
PIN DESCRIPTIONS
A0-A11 BA0, BA1 I/O0 to I/O15 CLK CKE CS RAS CAS Address Input Bank Select Address Data I/O System Clock Input Clock Enable Chip Select Row Address Strobe Command Column Address Strobe Command WE LDQM UDQM Vcc GND VccQ GNDQ NC Write Enable Lower Bye, Input/Output Mask Upper Bye, Input/Output Mask Power Ground Power Supply for I/O Pin Ground for I/O Pin No Connection
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev.C 04/16/03
1
IS42S16400A
ISSI
®
GENERAL DESCRIPTION
The 64Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 3.3V memory systems containing 67,108,864 bits. Internally configured as a quad-bank DRAM with a synchronous interface. Each 16,777,216-bit bank is organized as 4,096 rows by 256 columns by 16 bits. The 64Mb SDRAM includes an AUTO REFRESH MODE, and a power-saving, power-down mode. All signals are registered on the positive edge of the clock signal, CLK. All inputs and outputs are LVTTL compatible. The 64Mb SDRAM has the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time and the capability to randomly change column addresses on each clock cycle during burst access. A self-timed row precharge initiated at the end of the burst sequence is available with the AUTO PRECHARGE function enabled. Precharge one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, random-access operation. SDRAM read and write accesses are burst oriented starting at a selected location and continuing for a programmed number of locations in a programmed sequence. The registration of an ACTIVE command begins accesses, followed by a READ or WRITE command. The ACTIVE command in conjunction with address bits registered are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A11 select the row). The READ or WRITE commands in conjunction with address bits registered are used to select the starting column location for the burst access. Programmable READ or WRITE burst lengths consist of 1, 2, 4 and 8 locations or full page, with a burst terminate option.
FUNCTIONAL BLOCK DIAGRAM
CLK CKE CS RAS CAS WE A11
DQM COMMAND DECODER & CLOCK GENERATOR
DATA IN BUFFER
16 16
MODE REGISTER
11
REFRESH CONTROLLER
I/O 0-15
SELF REFRESH CONTROLLER
A10
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 BA0 BA1
11
DATA OUT BUFFER
16 16
Vcc/VccQ GND/GNDQ
REFRESH COUNTER
4096 4096 4096 4096
ROW DECODER
MULTIPLEXER
MEMORY CELL ARRAY
11
ROW ADDRESS LATCH
11
ROW ADDRESS BUFFER
BANK 0
SENSE AMP I/O GATE
COLUMN ADDRESS LATCH
8
256K (x 16)
BANK CONTROL LOGIC
BURST COUNTER
COLUMN DECODER
COLUMN ADDRESS BUFFER
8
2
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev.C 04/16/03
IS42S16400A
ISSI
Type Input Pin Function (In Detail) Address Inputs: A0-A11 are sampled during the ACTIVE command (row-address A0-A11) and READ/WRITE command (A0-A7 with A10 defining auto precharge) to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine if all banks are to be precharged (A10 HIGH) or bank selected by BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD MODE REGISTER command. Input Pin Input Pin Input Pin Bank Select Address: BA0 and BA1 defines which bank the ACTIVE, READ, WRITE or PRECHARGE command is being applied. CAS, in conjunction with the RAS and WE, forms the device command. See the "Command Truth Table" for details on device commands.
®
PIN FUNCTIONS
Symbol A0-A11 Pin No. 23 to 26 29 to 34 22, 35
BA0, BA1 CAS CKE
20, 21 17 37
The CKE input determines whether the CLK input is enabled. The next rising edge of the CLK signal will be valid when is CKE HIGH and invalid when LOW. When CKE is LOW, the device will be in either power-down mode, clock suspend mode, or self refresh mode. CKE is an asynchronous input. CLK is the master clock input for this device. Except for CKE, all inputs to this device are acquired in synchronization with the rising edge of this pin. The CS input determines whether command input is enabled within the device. Command input is enabled when CS is LOW, and disabled with CS is HIGH. The device remains in the previous state when CS is HIGH. I/O0 to I/O15 are I/O pins. I/O through these pins can be controlled in byte units using the LDQM and UDQM pins. LDQM and UDQM control the lower and upper bytes of the I/O buffers. In read mode, LDQM and UDQM control the output buffer. When LDQM or UDQM is LOW, the corresponding buffer byte is enabled, and when HIGH, disabled. The outputs go to the HIGH impedance state when LDQM/UDQM is HIGH. This function corresponds to OE in conventional DRAMs. In write mode, LDQM and UDQM control the input buffer. When LDQM or UDQM is LOW, the corresponding buffer byte is enabled, and data can be written to the device. When LDQM or UDQM is HIGH, input data is masked and cannot be written to the device. RAS, in conjunction with CAS and WE, forms the device command. See the "Command Truth Table" item for details on device commands. WE, in conjunction with RAS and CAS, forms the device command. See the "Command Truth Table" item for details on device commands. VCCQ is the output buffer power supply. VCC is the device internal power supply. GNDQ is the output buffer ground. GND is the device internal ground.
CLK CS
38 19
Input Pin Input Pin
I/O0 to I/O15 LDQM, UDQM
2, 4, 5, 7, 8, 10, 11,13, 42, 44, 45, 47, 48, 50, 51, 53 15, 39
I/O Pin
Input Pin
RAS WE VCCQ VCC GND Q GND
18 16 3, 9, 43, 49 1, 14, 27 6, 12, 46, 52 28, 41, 54
Input Pin Input Pin Power Supply Pin Power Supply Pin Power Supply Pin Power Supply Pin
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev.C 04/16/03
3
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