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Details, datasheet, quote on part number:IS61LF51218D-9TQ
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Datasheet text preview:
IS61LF25632T/D/J IS61LF25636T/D/J IS61LF51218T/D/J
256K x 32, 256K x 36, 512K x 18 SYNCHRONOUS FLOW-THROUGH STATIC RAM
FEATURES
· Internal self-timed write cycle · Individual Byte Write Control and Global Write · Clock controlled, registered address, data and control · Interleaved or linear burst sequence control using MODE input · Three chip enable option for simple depth expansion and address pipelining · Common data inputs and data outputs · JEDEC 100-Pin TQFP and 119-pin PBGA package · Power Supply + 3.3V VDD + 3.3V or 2.5V VDDQ (I/0) · Snooze MODE for reduced-power standby · T version (three chip selects) · J version (PBGA Package with JTAG) · D version (two chip selects) · JTAG Boundary Scan for PBGA.
ISSI
OCTOBER 2002
®
DESCRIPTION
The ISSI IS61LF25632, IS61LF25636, and IS61LF51218 are high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance and memories for commucation and networking applications. The IS61LF25632 is organized as 262,144 words by 32 bits and the IS61LF25636 is organized as 262,144 words by 36 bits. The IS61LF51218 is organized as 524,288 words by 18 bits. Fabricated with ISSI's advanced CMOS technology, the device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers that are controlled by a positive-edgetriggered single clock input. Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be from one to four bytes wide as controlled by the write control inputs. Separate byte enables allow individual bytes to be written. Byte write operation is performed by using byte write enable (BWE).input combined with one or more individual byte write signals (BWx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the byte write controls. Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally and controlled by the ADV (burst address advance) input pin. The mode pin is used to select the burst sequence order, Linear burst is achieved when this pin is tied LOW. Interleave burst is achieved when this pin is tied HIGH or left floating.
FAST ACCESS TIME
Symbol tKQ tKC Parameter Clock Access Time Cycle Time Frequency 6.5 6.5 7.5 133 7.5 7.5 8.5 117 Units ns ns MHz
Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. A 10/06/02
1
IS61LF25632T/D/J IS61LF25636T/D/J
BLOCK DIAGRAM
IS61LF51218T/D/J
ISSI
A0'
®
MODE Q0
CLK
CLK
A0
BINARY COUNTER
ADV ADSC ADSP CE CLR Q1 A1' A1
256K x 32; 256K x 36; 512K x 18 MEMORY ARRAY
Q 16/17 18/19
18/19 A D
ADDRESS REGISTER
CE CLK 32, 36, or 18 32, 36, or 18
GW BWE BWd (x32/x36)
DQd BYTE WRITE REGISTERS
CLK
D
Q
BWc (x32/x36)
D DQc Q BYTE WRITE REGISTERS CLK
BWb (x32/x36/x18)
DQb BYTE WRITE REGISTERS
CLK
D
Q
BWa (x32/x36/x18)
D DQa Q BYTE WRITE REGISTERS CLK
CE (T,D) CE2 (T,D) CE2 (T) D Q
4
ENABLE REGISTER
CE CLK
INPUT REGISTERS
CLK OE
32, 36, or 18 DQa - DQd
D
Q
ENABLE DELAY REGISTER
CLK
OE
2
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. A 10/06/02
IS61LF25632T/D/J IS61LF25636T/D/J
PIN CONFIGURATION
IS61LF51218T/D/J
ISSI
100-Pin TQFP (D Version)
A A CE CE2 BWd BWc BWb BWa A VDD GND CLK GW BWE OE ADSC ADSP ADV A A
®
119-pin PBGA (Top View) (D Version)
1 A VDDQ B NC C NC D DQc E DQc F VDDQ G DQc H DQc J VDDQ K DQd L DQd M VDDQ N DQd P DQd R NC T NC U VDDQ
2
3
4
5
6
7
A CE2 A NC DQc DQc DQc DQc VDD DQd DQd DQd DQd NC A NC NC
A A A GND GND GND BWc GND NC GND BWd GND GND GND MODE A NC
ADSP ADSC VDD NC CE OE ADV GW VDD CLK NC BWE A1 A0 VDD A NC
A A A GND GND GND BWb GND NC GND BWa GND GND GND GND A NC
A A A NC DQb DQb DQb DQb VDD DQa DQa DQa DQa NC A NC NC
VDDQ NC NC DQb DQb VDDQ DQb DQb VDDQ DQa DQa VDDQ DQa DQa NC ZZ VDDQ
NC DQc DQc VDDQ GND DQc DQc DQc DQc GND VDDQ DQc DQc NC VDD NC GND DQd DQd VDDQ GND DQd DQd DQd DQd GND VDDQ DQd DQd NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
MODE A A A A A1 A0 NC NC GND VDD NC NC A A A A A A A
NC DQb DQb VDDQ GND DQb DQb DQb DQb GND VDDQ DQb DQb GND NC VDD ZZ DQa DQa VDDQ GND DQa DQa DQa DQa GND VDDQ DQa DQa NC
256K x 32
256K x 32
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs Synchronous Clock Synchronous Processor Address Status Synchronous Controller Address Status Synchronous Burst Address Advance Synchronous Byte Write Enable Synchronous Byte Write Enable ZZ GW CE, CE2 OE DQa-DQd MODE VDD GND VDDQ Synchronous Global Write Enable Synchronous Chip Enable Output Enable Synchronous Data Input/Output Burst Sequence Mode Selection +3.3V Power Supply Ground Isolated Output Buffer Supply: +3.3V or 2.5V Snooze Enable
A CLK ADSP ADSC ADV BWa-BWd BWE
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev.A 10/06/02
3
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