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Part: IS61LPD25632T-166TQI
Category:
Memory
-> SRAM
-> Sync. SRAM
Description: 256Kx32
Company: Integrated Silicon Solution
Datasheet: Download IS61LPD25632T-166TQI datasheet File size : 223 kB
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Datasheet text preview:
IS61LPD25632T/D/J IS61LPD25636T/D/J IS61LPD51218T/D/J
256K x 32, 256K x 36, 512K x 18 SYNCHRONOUS PIPELINED, DOUBLE-CYCLE DESELECT STATIC RAM
FEATURES
· Internal self-timed write cycle · Individual Byte Write Control and Global Write · Clock controlled, registered address, data and control · Linear burst sequence control using MODE input · Three chip enable option for simple depth expansion and address pipelining · Common data inputs and data outputs · JEDEC 100-Pin TQFP and 119-pin PBGA package · Power Supply +3.3V VDD +3.3V or 2.5 VDDQ (I/O) · Auto Power-down during deselect · Double cycle deselect · Snooze MODE for reduced-power standby · JTAG Boundary Scan for PBGA package · T Version (three chips selects) · D Version (two chips selects) · J Version (PBGA Package with JTAG)
ISSI
APRIL 2003
®
DESCRIPTION The ISSI IS61LPD25632T/D/J, IS61LPD25636T/D/J, and
IS61LPD51218T/D/J are high-speed, low-power synchronous static RAMs designed to provide burstable, highperformance memory for communication and networking applications. The IS61LPD25632T/D/J is organized as 262,144 words by 32 bits and the IS61LPD25636T/D/J is organized as 262,144 words by 36 bits. The IS61LPD51218T/ D/J is organized as 524,288 words by 18 bits. Fabricated with ISSI's advanced CMOS technology, the device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input. Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be one to four bytes wide as controlled by the write control inputs. Separate byte enables allow individual bytes to be written. Byte write operation is performed by using byte write enable (BWE). Input combined with one or more individual byte write signals (BWx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the byte write controls. Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally and controlled by the ADV (burst address advance) input pin. The mode pin is used to select the burst sequence order. Linear burst is achieved when this pin is tied LOW. Interleave burst is achieved when this pin is tied HIGH or left floating.
FAST ACCESS TIME
Symbol tKQ tKC Parameter Clock Access Time Cycle Time Frequency -250 2.6 4 250 -225 2.8 4.4 225 -200 3.1 5 200 -166 3.5 6 166 Units ns ns MHz
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. A 04/01/03
1
IS61LPD25632T/D/J, IS61LPD25636T/D/J, IS61LPD51218T/D/J
BLOCK DIAGRAM
ISSI
®
MODE Q0 A0'
CLK
CLK
A0
BINARY COUNTER
ADV ADSC ADSP CE CLR Q1 A1' A1
256Kx32; 256Kx36; 512Kx18 MEMORY ARRAY
16/17 18/19 Q
18/19 A D
ADDRESS REGISTER
CE CLK 32, 36, or 18 32, 36, or 18
GW BWE BWd (x32/x36)
DQd BYTE WRITE REGISTERS
CLK
D
Q
BWc (x32/x36)
D DQc Q BYTE WRITE REGISTERS CLK
BWb (x32/x36/x18)
DQb BYTE WRITE REGISTERS
CLK
D
Q
BWa (x32/x36/x18)
D DQa Q BYTE WRITE REGISTERS CLK
CE (T,D) CE2 (T,D) CE2 (T) D Q
4
ENABLE REGISTER
CE CLK
INPUT REGISTERS
CLK
OUTPUT REGISTERS
CLK OE
32, 36, or 18 DQa - DQd
D
Q
ENABLE DELAY REGISTER
CLK
OE
2
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. A 04/01/03
IS61LPD25632T/D/J, IS61LPD25636T/D/J, IS61LPD51218T/D/J
PIN CONFIGURATION
119-pin PBGA (D Version) (Top View)
1 A VDDQ B NC C NC D DQc E DQc F VDDQ G DQc H DQc J VDDQ K DQd L DQd M VDDQ N DQd P DQd R NC T NC U VDDQ NC NC NC NC NC VDDQ NC A A A NC ZZ A MODE VDD NC A NC NC GND A0 GND NC DQa DQd GND A1 GND DQa DQa DQd GND DQd DQd GND BWd CLK NC BWE GND BWa GND DQa DQa DQa DQa DQa VDDQ VDD NC VDD NC VDD VDDQ DQc GND DQc DQc GND BWc DQc GND NC GND NC CE OE ADV GW GND GND GND BWb GND NC DQb DQb DQb DQb DQb DQb VDDQ DQb DQb A A VDD A A NC CE2 A A A 2 3 4 5 6 7
ISSI
®
ADSP ADSC
A A
A A
VDDQ NC
256K x 32
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs Synchronous Clock Synchronous Processor Address Status Synchronous Controller Address Status Synchronous Burst Address Advance Individual Byte Write Enable Synchronous Byte Write Enable GW CE, CE2, CE2 OE DQa-DQd MODE VDD GND VDDQ ZZ DQPa-DQPd Synchronous Global Write Enable Synchronous Chip Enable Output Enable Synchronous Data Input/Output Burst Sequence Mode Selection +3.3V Power Supply Ground Isolated Output Buffer Supply: +3.3V or 2.5V Snooze Enable Parity Data I/O
A CLK ADSP ADSC ADV BWa-BWd BWE
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. A 04/01/03
3
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