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Part: IS62LV2568LL
Category:
Memory
-> SRAM
-> Async. SRAM
-> 2 Mb
Description: Low Power And Low VCC CMOS Static RAM: 256kx8
Company: Integrated Silicon Solution
Datasheet: Download IS62LV2568LL datasheet File size : 104 kB
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Datasheet text preview:
IS62LV2568LL
256K x 8 LOW POWER and LOW Vcc CMOS STATIC RAM
FEATURES
· Access times of 70 and 85 ns · CMOS low power operation: -- 120 mW (typical) operating -- 6 µW (typical) standby · Low data retention voltage: 2V (min.) · Output Enable (OE) and two Chip Enable (CE1 and CE2) inputs for ease in applications · TTL compatible inputs and outputs · Fully static operation: -- No clock or refresh required · Single 2.5V to 3.0V power supply · Available in 32-pin TSOP (Type I), STSOP (Type I), and 36-pin mini BGA
ISSI
DESCRIPTION
®
APRIL 2000
The ISSI IS62LV2568LL is a low voltage, 262,144 words by 8 bits, CMOS SRAM. It is fabricated using ISSI's low voltage, six transistor (6T), CMOS technology. The device is targeted to satisfy the demands of the state-of-the-art technologies such as cell phones and pagers. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Additionally, easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. The IS62LV2568LL is available in 32-pin TSOP (Type I), STSOP (Type I), and 36-pin mini BGA.
FUNCTIONAL BLOCK DIAGRAM
A0-A17
DECODER
256K x 8 MEMORY ARRAY
VCC GND I/O DATA CIRCUIT
I/O0-I/O7
COLUMN I/O
CE1 CE2 OE WE CONTROL CIRCUIT
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. B 05/03/00
1
IS62LV2568LL
PIN CONFIGURATION 36-pin mini BGA (B)
1 2 3 4 5 6
ISSI
PIN DESCRIPTIONS
A0-A17 CE1 CE2 OE WE Address Inputs Chip Enable 1 Input Chip Enable 2 Input Output Enable Input Write Enable Input Input/Output No Connection Power Ground
®
A B C D E F G H
A0 I/O4 I/O5 GND Vcc I/O6 I/O7 A9
A1 A2
CE2 WE NC
A3 A4 A5
A6 A7
A8 I/O0 I/O1 Vcc GND
I/O0-I/O7 NC Vcc GND
NC OE A10 CE1 A11
A17 A16 A12 A15 A13
I/O2 I/O3 A14
32-Pin TSOP (Type I), STSOP (Type I)
A11 A9 A8 A13 WE CE2 A15 VCC A17 A16 A14 A12 A7 A6 A5 A4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3
2
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. B 05/03/00
IS62LV2568LL
ISSI
CE1 H X L L L CE2 X L H H H OE X X H L X I/O Operation High-Z High-Z High-Z DOUT DIN Vcc Current ISB1, ISB2 ISB1, ISB2 ICC ICC ICC X X H H L
®
TRUTH TABLE
Mode Not Selected (Power-down) Output Disabled Read Write WE
OPERATING RANGE
Range Commercial Industrial Ambient Temperature 0°C to +70°C 40°C to +85°C VCC 2.5V to 3.0V 2.5V to 3.0V
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VT E R M VCC TB I A S TSTG PT Parameter Terminal Voltage with Respect to GND Vcc related to GND Temperature Under Bias Storage Temperature Power Dissipation Value 0.5 to Vcc + 0.5 0.3 to +4.6 40 to +85 65 to +150 0.7 Unit V V °C °C W
Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
CAPACITANCE(1,2)
Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 6 8 Unit pF pF
Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 3.0V.
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. B 05/03/00
3
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