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Part: IS64LP25618-166BA1
Category:
Memory
-> SRAM
-> Sync. SRAM
Description: 256Kx18
Company: Integrated Silicon Solution
Datasheet: Download IS64LP25618-166BA1 datasheet File size : 133 kB
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Datasheet text preview:
IS64LP12832 IS64LP12836, IS64LP25618
128K x 32, 128K x 36, 256K x 18 SYNCHRONOUS PIPELINED STATIC RAM
FEATURES
· Internal self-timed write cycle · Individual Byte Write Control and Global Write · Clock controlled, registered address, data and control · Interleaved or linear burst sequence control using MODE input · Three chip enables for simple depth expansion and address pipelining · Common data inputs and data outputs · JEDEC 100-Pin TQFP and 119-pin PBGA package · Power-down snooze mode · Power Supply + 3.3V VDD + 3.3V OR 2.5V VDDQ (I/O) · Temperature offerings Option A1: -400 C to +850 C Option A2: -400 C to +1050 C Option A3: -400 C to +1250 C
ISSI
®
ADVANCED INFORMATION JANUARY 2003
DESCRIPTION The ISSI IS64LP12832, IS64LP12836, and IS64LP25618
are high-speed synchronous static RAMs designed to provide high-performance memory with burst for highspeed networking and communication applications. IS64LP12832 is organized as 131,072 words by 32 bits. IS64LP12836 is organized as 131,072 words by 36 bits. IS64LP25618 is organized as 262,144 words by 18 bits. The IS64LP12832, IS64LP12836, and IS64LP25618 are fabricated with ISSI's advanced CMOS technology. These devices integrate a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input. Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be from one to four bytes wide as controlled by the write control inputs. Separate byte enables allow individual bytes to be written. BW1 controls DQa, BW2 controls DQb, BW3 controls DQc, BW4 controls DQd, conditioned by BWE being LOW. A LOW on GW input would cause all bytes to be written. Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally and controlled by the ADV (burst address advance) input pin. The mode pin is used to select the burst sequence order, Linear burst is achieved when this pin is tied LOW. Interleave burst is achieved when this pin is tied HIGH or left floating.
FAST ACCESS TIME
Symbol tKQ tKC Parameter Clock Access Time Cycle Time Frequency -166 3.5 6 166 -150 3.8 6.7 150 Units ns ns MHz
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the l a t e s t version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. 00A 01/20/03
1
IS64LP12832 IS64LP12836, IS64LP25618
BLOCK DIAGRAM
MODE Q0 A0'
ISSI
A0
®
CLK
CLK
BINARY COUNTER
ADV ADSC ADSP CE CLR Q1 A1' A1
128K x 32/128K x 36, 256K x 18 MEMORY ARRAY
Q 16/17 18/19
A
17/18
D
ADDRESS REGISTER
CE CLK 32 or 36 or 18 32 or 36 or 18
GW BWE BW4 (x32/ x36)
DQd BYTE WRITE REGISTERS
CLK
D
Q
BW3 (x32/ x36)
D DQc Q BYTE WRITE REGISTERS CLK
BW2 (x32/ x36/ x18)
DQb BYTE WRITE REGISTERS
CLK
D
Q
BW1 (x32/ x36/ x18)
D DQa Q BYTE WRITE REGISTERS CLK
CE CE2 CE2 D Q
4
ENABLE REGISTER
CE CLK
INPUT REGISTERS
CLK
OUTPUT REGISTERS
CLK
32 or 36 or 18 DQa-d OE
D
Q
ENABLE DELAY REGISTER
CLK
OE
2
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. 00A 01/20/03
IS64LP12832 IS64LP12836, IS64LP25618
PIN CONFIGURATION
119-pin PBGA (Top View) 100-Pin TQFP
ISSI
A A CE CE2 BW4 BW3 BW2 BW1 CE2 VDD GND CLK GW BWE OE ADSC ADSP ADV A A
®
1 A VDDQ B NC C NC D DQc1 E DQc2 F VDDQ G DQc5 H DQc7 J VDDQ K DQd1 L DQd4 M VDDQ N DQd6 P DQd8 R NC T NC U VDDQ
2
3
4
5
6
7
6 A6 CE2 A7 7 NC DQc3 DQc4 DQc6 DQc8 VDD DQd2 DQd3 DQd5 DQd7 NC A5 NC NC
4 A4 A3 3 A2 2 GND GND GND BW3 GND NC GND BW4 GND GND GND MODE A10 10 NC
ADSP ADSC VDD NC CE OE ADV GW VDD CLK NC BWE A1 A0 VDD 11 A11 NC
8 A8 A9 9 A12 12 GND GND GND BW2 GND NC GND BW1 GND GND GND NC A14 14 NC
16 A16 CE2 A15 15 NC DQb6 DQb5 DQb4 DQb2 VDD DQa7 DQa5 DQa4 DQa3 NC A13 13 NC NC
VDDQ NC NC DQb8 DQb7 VDDQ DQb3 DQb1 VDDQ DQa8 DQa6 VDDQ DQa2 DQa1 NC ZZ VDDQ
NC DQc DQc VDDQ GND DQc DQc DQc DQc GND VDDQ DQc DQc NC VDD NC GND DQd DQd VDDQ GND DQd DQd DQd DQd GND VDDQ DQd DQd NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC DQb DQb VDDQ GND DQb DQb DQb DQb GND VDDQ DQb DQb GND NC VDD ZZ DQa DQa VDDQ GND DQa DQa DQa DQa GND VDDQ DQa DQa NC
128K x 32
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs Synchronous Clock Synchronous Processor Address Status Synchronous Controller Address Status Synchronous Burst Address Advance Individual Byte Write Enable Synchronous Byte Write Enable GW CE, CE2, CE2 OE DQa-DQd MODE VDD GND VDDQ ZZ Synchronous Global Write Enable Synchronous Chip Enable Output Enable Synchronous Data Input/Output Burst Sequence Mode Selection +3.3V Power Supply Ground Isolated Output Buffer Supply: +3.3V or 2.5V Snooze Enable
A CLK ADSP ADSC ADV BW1-BW4 BWE
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. 00A 01/20/03
MODE A A A A A1 A0 NC NC GND VDD NC NC A A A A A A A
3
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