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Details, datasheet, quote on part number:IS93C46A-3ZI
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Datasheet text preview:
IS93C46A IS93C56A IS93C66A
ISSI
2003
®
1,024/2,048/4,096-BIT SERIAL ELECTRICALLY ERASABLE PROM FEBRUARY
FEATURES
· Industry-standard Microwire Interface -- Non-volatile data storage -- Low voltage operation: Vcc = 2.5V to 5.5V -- Full TTL compatible inputs and outputs -- Auto increment for efficient data dump · User Configured Memory Organization -- By 16-bit or by 8-bit · Hardware and software write protection -- Defaults to write-disabled state at power-up -- Software instructions for write-enable/disable · Enhanced low voltage CMOS E2PROM technology · Versatile, easy-to-use Interface -- Self-timed programming cycle -- Automatic erase-before-write -- Programming status indicator -- Word and chip erasable -- Chip select enables power savings · Durable and reliable -- 40-year data retention after 1M write cycles -- 1 million write cycles -- Unlimited read cycles -- Schmitt-trigger inputs · Industrial and Automotive Temperature Grade
DESCRIPTION
The IS93C46A/56A/66A is a low-cost 1kb/2kb/4kb non-volatile, ISSI ® serial EEPROM. It is fabricated using an enhanced CMOS design and process. The IS93C46A/56A/66A contain powerefficient read/write memory, and organization of either 128/256/512 bytes of 8 bits or 64/128/256 words of 16 bits. When the ORG pin is connected to Vcc or left unconnected, x16 is selected; when it is connected to ground, x8 is selected. The IS93C46A/56A/66A is fully backwards compatible with IS93C46/56/66. An instruction set defines the operation of the devices, including read, write, and mode-enable functions. To protect against inadvertent data modification, all erase and write instructions are accepted only while the device is write-enabled. A selected x8 byte or x16 word can be modified with a single WRITE or ERASE instruction. Additionally, the two instructions WRITE ALL or ERASE ALL can program the entire array. Once a device begins its self-timed program procedure, the data out pin (Dout) can indicate the READY/ BUSY status by raising chip select (CS). The selftimed write cycle includes an automatic erasebefore-write capability. The device can output any number of consecutive bytes/words using a single READ instruction.
FUNCTIONAL BLOCK DIAGRAM
DUMMY BIT R/W AMPS INSTRUCTION DECODE, CONTROL, AND CLOCK GENERATION ADDRESS REGISTER ADDRESS DECODER EEPROM ARRAY 128/256/512x16 64/128/256/x8
DATA REGISTER DIN INSTRUCTION REGISTER
DOUT
CS
SK
WRITE ENABLE
HIGH VOLTAGE GENERATOR
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. B 01/20/03
1
IS93C46A
IS93C56A
IS93C66A
ISSI
8-Pin JEDEC SOIC "GR"
ORG GND DOUT DIN
®
PIN CONFIGURATIONS
8-Pin DIP, 8-Pin TSSOP
CS SK DIN DOUT 1 2 3 4 8 7 6 5 VCC NC ORG GND
8-Pin JEDEC SOIC "G"
NC VCC CS SK 1 2 3 4 8 7 6 5
CS SK DIN DOUT
1 2 3 4
8 7 6 5
VCC NC ORG GND
(Rotated)
PIN DESCRIPTIONS
CS SK DIN DOUT ORG NC Vcc GND Chip Select Serial Data Clock Serial Data Input Serial Data Output Organization Select Not Connected Power Ground
instruction begins with a start bit of the logical "1" or HIGH. Following this are the opcode (2 bits), address field (6, 7, 8, or 9 bits), and data, if appropriate. The clock signal may be held stable at any moment to suspend the device at its last state, allowing clockspeed flexibility. Upon completion of bus communication, CS would be pulled LOW. The device then would enter Standby mode if no internal programming is underway.
Read (READ)
The READ instruction is the only instruction that outputs serial data on the DOUT pin. After the read instruction and address have been decoded, data is transferred from the selected memory register into a serial shift register. (Please note that one logical "0" bit precedes the actual 8 or 16-bit output data string.) The output on DOUT changes during the low-to-high transitions of SK (see Figure 3).
Applications
The IS93C46A/56A/66A is very popular in many highvolume applications which require low-power, lowdensity storage. Applications using this device include industrial controls, networking, and numerous other consumer electronics.
Low Voltage Read
The IS93C46A/56A/66A have been designed to ensure that data read operations are reliable in low voltage environments. They provide accurate operation with Vcc as low as 2.5V.
Endurance and Data Retention
The IS93C46A/56A/66A is designed for applications requiring up to 1M programming cycles (WRITE, WRALL, ERASE and ERAL). It provides 40 years of secure data retention without power after the execution of 1M programming cycles.
Auto Increment Read Operations
In the interest of memory transfer operation applications, the IS93C46A/56A/66A has been designed to output a continuous stream of memory content in response to a single read operation instruction. To utilize this function, the system asserts a read instruction specifying a start location address. Once the 8 or16 bits of the addressed register have been clocked out, the data in consecutively higher address locations is output. The address will wrap around continuously with CS HIGH until the chip select (CS) control pin is brought LOW. This allows for single instruction data dumps to be executed with a minimum of firmware overhead.
Device Operations
The IS93C46A/56A/66A are controlled by a set of instructions which are clocked-in serially on the Din pin. Before each low-to-high transition of the clock (SK), the CS pin must have already been raised to HIGH, and the Din value must be stable at either LOW or HIGH. Each
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Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. B 02/20/03
IS93C46A
IS93C56A
IS93C66A
ISSI
Write All (WRALL)
®
Write Enable (WEN)
The write enable (WEN) instruction must be executed before any device programming (WRITE, WRALL, ERASE, and ERAL) can be done. When Vcc is applied, this device powers up in the write disabled state. The device then remains in a write disabled state until a WEN instruction is executed. Thereafter, the device remains enabled until a WDS instruction is executed or until Vcc is removed. (See Figure 4.) (Note: Chip select must remain LOW until Vcc reaches its operational value.)
The write all (WRALL) instruction programs all registers with the data pattern specified in the instruction. As with the WRITE instruction, the falling edge of CS must occur to initiate the self-timed programming cycle. If CS is then brought HIGH after a minimum wait of 250 ns (tCS), the DOUT pin indicates the READY/BUSY status of the chip (see Figure 6).
Write Disable (WDS)
The write disable (WDS) instruction disables all programming capabilities. This protects the entire device against accidental modification of data until a WEN instruction is executed. (When Vcc is applied, this part powers up in the write disabled state.) To protect data, a WDS instruction should be executed upon completion of each programming operation.
Write (WRITE)
The WRITE instruction includes 8 or 16 bits of data to be written into the specified register. After the last data bit has been applied to DIN, and before the next rising edge of SK, CS must be brought LOW. If the device is writeenabled, then the falling edge of CS initiates the selftimed programming cycle (see WEN). If CS is brought HIGH, after a minimum wait of 250 ns (5V operation) after the falling edge of CS (tCS) DOUT will indicate the READY/BUSY status of the chip. Logical "0" means programming is still in progress; logical "1" means the selected register has been written, and the part is ready for another instruction (see Figure 5). The READY/ BUSY status will not be available if: a) The CS input goes HIGH after the end of the self-timed programming cycle, tWP; or b) Simultaneously CS is HIGH, Din is HIGH, and SK goes HIGH, which clears the status flag.
Erase Register (ERASE)
After the erase instruction is entered, CS must be brought LOW. The falling edge of CS initiates the self-timed internal programming cycle. Bringing CS HIGH after a minimum of tCS, will cause DOUT to indicate the READ/BUSY status of the chip: a logical "0" indicates programming is still in progress; a logical "1" indicates the erase cycle is complete and the part is ready for another instruction (see Figure 8).
Erase All (ERAL)
Full chip erase is provided for ease of programming. Erasing the entire chip involves setting all bits in the entire memory array to a logical "1" (see Figure 9).
INSTRUCTION SET - IS93C46A
8-bit Organization (ORG = GND) Address (1) Input Data (A6 -A 0 ) 11xxxxx (A6 -A 0 ) 01xxxxx 00xxxxx (A6 -A 0 ) 10xxxxx -- -- (D7-D0) (D7-D0) -- -- --
(3) (3)
Instruction READ WEN (Write Enable) WRITE
Start Bit 1 1 1 1 1 1 1
OP Code 10 00 01 00 00 11 00
16-bit Organization (ORG = Vcc) Address (1) Input Data (A5 -A 0 ) 11xxxx (A5 -A 0 ) 01xxxx 00xxxx (A5 -A 0 ) 10xxxx -- -- (D15-D0) (D15-D0) -- -- --
(2) (2)
WRALL (Write All Registers) WDS (Write Disable) ERASE ERAL (Erase All Registers)
Notes: 1. x = Don't care bit. 2. If input data is not 16 bits exactly, the last 16 bits will be taken as input data. 3. If input data is not 8 bits exactly, the last 8 bits will be taken as input data.
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. B 02/20/03
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