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Details, datasheet, quote on part number:IXDP610PI
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Datasheet text preview:
IXDP 610
Bus Compatible Digital PWM Controller, IXDP 610
Description The IXDP610 Digital Pulse Width Modulator (DPWM) is a programmable CMOS LSI device which accepts digital pulse width data from a microprocessor and generates two complementary, non-overlapping, pulse width modulated signals for direct digital control of switching power bridge. The DPWM is designed to be operated under the direct control of a microprocessor and interfaces easily with most standard microprocessor and microcomputer buses. The IXDP610 is packaged in an 18-Pin slim DP. The PWM waveform generated by the IXDP610 results from comparing the output of the Pulse Width counter to the number stored in the Pulse Width Latch (see below). A programmable "dead-time" is incorporated into the PWM waveform. The Dead-Time Logic disables both outputs on each transition of the Comparator output for the required dead-time interval. The output stage provides complementary PWM output signals capable of sinking and sourcing 20 mA at TTL voltage levels. The Output Disable logic can be activated either by software or hardware. This facilitates cycle-by-cycle current-limit, shortcircuit, over-temperature, and desaturation protection schemes. The IXDP610 is capable of operating at PWM frequencies from zero to 390kHz; the dead-time is programmable from zero to 14 clock cycles (0 to 11 % of the PWM cycle), which allows operation with fast power MOSFETs, IGBTs, and bipolar power transistors. A trade-off between PWM frequency and resolution is provided by selecting the counter resolution to be 7-bit or 8-bit. The 20 mA output drive makes the IXDP610 capable of directly driving opto isolators and Smart Power devices. The fast response to pulse width commands is achieved by instantaneous change of the outputs to correspond to the new command. This eliminates the one-cycle delay usually associated with other digital PWM implementations. Features
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Microcomputer bus compatible Two complementary outputs for direct control of a switching power bridge Dynamically programmable pulse width ranges from 0 to 100 % Two modes of operation: 7-bit or 8bit resolution Switching frequency range up to 390 kHz Programmable Dead-time Counter prevents switching overlap Cycle-by-Cycle disable input to protect against over-current, overtemperature, etc. Outputs may be disabled under software control Special locking bit prevents damage to the stage in the event of a software failure 18-pin slim DIP package
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Dimensions in inch and mm 18-Pin Slim DIP
Symbol VCC VIN Vout PD Tstg
1
Definition Supply voltage Input voltage Output voltage Maximum power dissipation Storage temperature range
Maximum Ratings -0.3 ... 5.5 -0.3 ... VCC + 0.3 -0.3 ... VCC + 0.3 500 -40 ... 125 V V V mW °C
© 2001 IXYS/DEI All rights reserved
IXDP 610
Symbol Definition Operating Range Supply voltage Operating free air temperature Maximum Ratings min. VCC TA Symbol 4.5 -40 max. 5.5 85 V °C Numbers in the Fig. 3 to 6 corresponding to the time values on the bottom left of this page.
Definition/Condition Characteristic Values (Over operating range, unless otherwise specified) min. typ. max. Input High Voltage Input Low Voltage Input Hysteresis ODIS ODIS ODIS 3.8 -0.3 0.3 2.4 0.4 2.0 -0.3 -10 -0.1 3.5 0.5 VCC +0.3 V 1.2 V V V V Fig. 3 Write operation timing diagram
VIH(CMOS) VIL(CMOS) VH VOH VOL VIH(TTL) VIL(TTL) ILI ICC
Output High Voltage OUT1 IOH = -20 mA OUT2 Output Low Voltage Input High Voltage Input Low Voltage Input Leakage Current Power Supply Current Definition/Condition OUT1 IOL = 20 mA OUT2 All Inputs Except ODIS All Inputs Except ODIS All Inputs 0 < VI < VCC fCLK = 5 MHz VIH = VCC or 0
VCC +0.3 V 0.8 10 10 V µA mA
Fig. 4 Output disable to outputs off timing
Symbol
Characteristic Values (TA = 25°C, VCC = 5 V ± 10 %, C1 = 50 pF) -40...85°C
typ. min. 5 max. ns
WR OUT 1 or OUT2
No. see Fig. 3-6 1 tAVWL SEL Stable to WR Low
2 3 4 5 6 7 8 9
tWHAX tSLWL tWHSH tWLWH tDVWH tWHDX fCLK tCLCH tCHCL
SEL Stable after WR High CS Low to WR Low CS High after WR High WR Pulse Width Data Valid to WR High Data Held after WR High Clock Frequency Clock Pulse Duration Low High CLK to Output when Writing to PW latch ODIS Low to Output Low WR High to Output Low When Writing Stop to the Control latch RST Low Time 10 5 0* 12.5 12.5 5+½TCLK** 20 30 8
10 5 5 20 5 20 0 12.5 12.5 5 50 60 5+TCLK 50 *
ns ns ns ns ns ns MHz ns ns ns ns ns Fig. 6 CLOCK to output when writing to PW latch
CLK <5ns 10 8 9 9 OUT1 OUT2 WR
Fig. 5 Stop to outputs off timing
1
2
3
10 tCHOV 11 tODLOL 12 tWHOL
13 tRLRH
*
50
ns
Output will change 1 rising CLOCK edge +5ns after WR (see Fig. 6) 2
** Tclk = 1/fclk
© 2001 IXYS/DEI All rights reserved
IXDP 610
Pin Description IXDP 610PI
D0 D1 D2 D3 D4 D5 D6 D7 GND
IXYS IXDP610PI
CS WR RST SEL ODIS CLK VCC OUT1 OUT2
Nomenclature of Digital PWM Controller
Sym. Pin Description D0 1
D1 D2 D3 D4 D5 D6 D7
2 3 4 5 6 7 8
DATA BUS - the data bus on the IXDP610 is configured for input only. Data to be written to the IXDP610 is placed on data lines D0 through D7 during a microprocessor write cycle. Data is accepted by the IXDP610 when CHIP SELECT is low and the WRITE input goes from a low to a high state. The SELECT input determines whether the data written to the IXDP610 will go to the Control latch or to the Pulse Width latch. D0 is the least significant bit and D7 is the most significant bit. CIRCUIT GROUND
SEL 15 SELECT-this input determines whether data written into the IXDP610 goes to the internal Pulse Width (PW) latch or to the Control latch. A zero on this input (low voltage) directs data to the PW latch; a one on this input (high voltage) directs data to the Control latch. RST 16 RESET-this asynchronous, active low input disables the outputs, chooses 8-bit count mode in the PWM counter, sets the clock to be "divided by 1", clears Lock bit, and sets the dead-time counter to 7. Asserting RESET writes a 01000111 binary to the Control latch. Asserting RESET is the only way in which the Lock bit in the control latch can be cleared. Writes to the control latch that occur after the lock bit has been set to a one, can only modify the Stop bit. Any writes to the control latch, while the RESET input is asserted, are ignored. RESET also clears the PW latch. W R 17 WRITE-a low-to-high transition on this input, when CHIP SELECT is low, causes data to be written to the selected IXDP610 latch. If SELECT is low, the data is written to the pulse width latch. If SELECT is high, the data is written to the control latch. CS 18 CHIP SELECT - this active low input enables the WRITE input so that data may be written into the IXDP610 latch selected by the SELECT input.
IXDP 610 P I IX DP 610 P I
(Example) IXYS Digital PWM Controller Package Type 18-Pin Plastic DIP Temperature Range Industrial (-40 to 85°C)
GND 9
OUT2 10 COMPLEMENTARY OUTPUTS OUT1 11 these two outputs provide the complementary PWM signals. The base period or cycle time of these outputs is determined by the CLOCK and the control latch. VCC 12 POWER SUPPLY (5 V ± 10 %)
CLK 13 CLOCK - the frequency of this input determines the PWM base frequency. CLK also drives the internal state machines. It has no effect on any data bus transactions. ODIS 14 OUTPUT DISABLE - asserting this Schmitt trigger input forces the complementary outputs to be immediately disabled (OUT1 and OUT2 are forced low). The complementary outputs will remain low as long as long as this input is asserted, and for the duration of the PWM cycle in which OUTPUT DISABLE goes from low to high; i.e., the complementary outputs are not re-enabled until the beginning of the next PWM cycle, and then only if OUTPUT DISABLE and the Stop bit in the Control latch are not asserted.
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© 2001 IXYS/DEI All rights reserved
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