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Details, datasheet, quote on part number:KT12872DRN3R
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Datasheet text preview:
128M X 72 REGISTERED DDR DIMM
DDR SDRAM FEMMA MODULE
1 Giga Byte (128M x 72) DDR SDRAM Low Profile Registered 184 Pin DIMM Preliminary
General Description:
This memory module is a high performance 1024 Megabyte Registered synchronous dynamic RAM module organized as 128M x 72 in a 184-pin Dual In-Line Memory Module (DIMM) package. The module utilizes thirty-six (36) 64M x4X4 DDR SDRAM (64ms Refresh) devices in a TSOP II 400 mil package. A 256 Byte Serial EEPROM contains the module configuration information. The EEPROM is configured to JEDEC specifications. These modules offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high rate with automatic column-address generation, interleave between internal banks in order to hide pre-charge time, and the capability to randomly change column address on each clock cycle during burst.
Features:
High density: Cycle time: 1024 MB (128M x 72) 7.5ns (133 MHz) 10ns (100 MHz) Data Rate: 266Mbit/sec/pin (133 MHz) 200Mbit/sec/pin (100 MHz) JEDEC Standard 184 Pin Registered SDRAM DDR DIMM PC1600 (DDR200) / PC2100 Single power supply of 2.5V ± 10% Serial Presence Detect SSTL2 Compatible I/O and Clock SSTL2 Registered Control & Address Lines On-board Differential PLL Clock Driver Auto Precharge and Auto Refresh Modes handled by SDRAM Devices Programmable Burst Type, Burst Length and CAS Latency of SDRAM devices Internal Pipeline Operation Fully Synchronous all signals registered on positive edge of system clock Data provided during Reads and Writes at twice the clock frequency Package Height: 1.20 inches
Kentron Technologies, Inc. 155 West Street Wilmington, MA 01887 Phone: 978/988-9100 Fax 978/988-5550 www.kentrontech.com
128M X 72 REGISTERED DDR DIMM
Operating Features:
The SDRAM DDR DIMM utilizes a differential clock input for the synchronization. Each operation of the SDRAM is determined by commands and all operations are referenced to a positive clock edge. CAS Latency defines the delay from when a Read Command is registered on a rising clock edge to when the data from the Read Command becomes available at the outputs. The CAS latency is expressed in terms of clock cycles. This specific DIMM supports 3 and 2 clock cycles. The burst mode is a very high-speed access mode utilizing an internal column address generator. Once a column address for the first access is set, following addresses are automatically generated by the internal column address counter. All control and address signals are registered on-board and hence delayed by one cycle in arriving at the SDRAMs. The clock signal is distributed to all SDRAMs via a zero delay PLL driver. Note that the PLL must be given enough clock cycles to stabilize before any operation can be given (minimum stabilization time equal to 1 ms).
Absolute Maximum Ratings*: Item
Supply voltage (VCC Relative to VSS) Input/Output Voltage Operating temperature Storage temperature Short circuit output current
Symbol
Vdd Vddq Topr Tstg Iout
Rating
-1 ~ 3.6 -1 ~ 3.6 70 -55 ~ 150 50
Unit
V V °C °C mA
* Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation should be restricted to the conditions as detailed in the sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions:
(Voltage referenced to Vdd. TA = 0 to 70 °C)
Item
Supply voltage Input high voltage Input low voltage Operating Temperature
Symbol
VCC VIH VIL TA
Min.
2.3 Vref +0.15 -0.3 0
Typ.
2.5 +25
Max.
2.7 Vref +0.3 0.8 70
Unit
V V V °C
Kentron Technologies, Inc. (978) 988-9100 Rev. (3/02)
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128M X 72 REGISTERED DDR DIMM
Capacitance:
(TA=25°C, Vdd=2.5V±0.2V)
Parameter Input capacitance (Address/ WE, CKE0, /CAS, RAS, /CS0~/CS3) Input capacitance (/DQMBs) Input capacitance (CK0) Input capacitance (DQS0~DQS7) Input/Output capacitance (DQ0~DQ63, CB0~CB7)
Symbol CIN CIN CIN CIN CI/O
Max. 8 11 4 11 11
Unit pF pF pF pF pF
DIMM Pinout:
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 Designation VREF DQ0 VSS DQ1 DQS0 DQ2 VDD DQ3 NC RESET/ VSS DQ8 DQ9 DQS1 VDDQ DU (CK1) DU (CK1)/ VSS DQ10 DQ11 CCKE0 VDDQ DQ16 DQ17 DQS2 VSS A9 DQ18 A7 VDDQ DQ19 A5 DQ24 VSS DQ25 DQS3 A4 VDD No. 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 Designation DQ26 DQ27 A2 VSS A1 CB0 CB1 VDD DQS8 A0 CB2 VSS CB3 BA1 DQ32 VDDQ DQ33 DQS4 DQ34 VSS BA0 DQ35 DQ40 VDDQ WE/ DQ41 CAS/ VSS DQS5 DQ42 DQ43 VDD NC, S2/ DQ48 DQ49 VSS DU (CK2)/ DU (CK2) No. 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 Designation VDDQ DQS6 DQ50 DQ51 VSS VDDID DQ56 DQ57 VDD DQS7 DQ58 DQ59 VSS NC SDA SCL VSS DQ4 DQ5 VDDQ DM0/DQS9 DQ6 DQ7 VSS NC NC A13 VDDQ DQ12 DQ13 DM1/DQS10 VDD DQ14 DQ15 CKE1 VDDQ BA2 DQ20 No. 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 Designation A12 VSS DQ21 A11 DM2/DQS11 VDD DQ22 A8 DQ23 VSS A6 DQ28 DQ29 VDDQ DM3/DQS12 A3 DQ30 VSS DQ31 CB4 CB5 VDDQ CK0 CK0 VSS DM8/DQS17 A10 CB6 VDDQ CB7 VSS DQ36 DQ37 VDD DM4/DQS13 DQ38 DQ39 VSS No. 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 Designation DQ44 RAS/ DQ45 VDDQ S0/ S1/ DM5/DQS14 VSS DQ46 DQ47 NC,S3/ VDDQ DQ52 DQ53 NC,FETEN VDD DM6/DQS15 DQ54 DQ55 VDDQ NC DQ60 DQ61 VSS DM7/DQS16 DQ62 DQ63 VDDQ SA0 SA1 SA2 VDDSPD
Kentron Technologies, Inc. (978) 988-9100 Rev. (3/02)
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