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Details, datasheet, quote on part number:KT12872SRN0R
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Datasheet text preview:
128M X 72 REGISTERED SDRAM DIMM
SDRAM FEMMA MODULE
1GByte (128M x 72) SDRAM Registered 168 Pin DIMM
General Description:
This memory module is a high performance 1024 Megabyte Registered synchronous dynamic RAM module organized as 128M x 72 in a 168 pin Dual In-Line Memory Module (DIMM) package. The module utilizes thirty-six (36) 16Mx4X4 SDRAM devices in a TSOP II 400 mil package. A 256 Byte Serial EEPROM contains the module configuration information. The EEPROM can be configured to a customer's specifications. These modules offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high rate with automatic column-address generation, interleave between internal banks in order to hide precharge time, and the capability to randomly change column address on each clock cycle during burst.
Features:
High density: 1024 MB (128M x 72) Cycle time: 10ns (100 MHz) JEDEC Standard 168 Pin Registered SDRAM DIMM Single power supply of 3.3V ± 10% Serial Presence Detect LVTTL Compatible I/O and Clock Registered Control Lines On-board PLL Clock Driver Program Burst Lengths and CAS Latency Auto Precharge and Auto Refresh Modes Programmable Burst Type, Burst Length and CAS Latency Internal Pipeline Operation Fully Synchronous all signals registered on positive edge of system clock Module Standard: FEMMATM Packaging Technology (Patented) Package Height: 1.50 inches
Kentron Technologies, Inc. 155 West Street Wilmington, MA 01887 Phone: (978) 988-9100 Fax (978) 988-5550 www.kentrontech.com
128M X 72 REGISTERED SDRAM DIMM
Operating Features:
The SDRAM DIMM utilizes a clock input for the synchronization. Each operation of the SDRAM is determined by commands and all operations are referenced to a positive clock edge. CAS Latency defines the delay from when a Read Command is registered on a rising clock edge to when the data from the Read Command becomes available at the outputs. The CAS latency is expressed in terms of clock cycles. This specific DIMM supports 3 and 2 clock cycles. The burst mode is a very high-speed access mode utilizing an internal column address generator. Once a column address for the first access is set, following addresses are automatically generated by the internal column address counter. All control and address signals are registered on-board and hence delayed by one cycle in arriving at the SDRAMs. The clock signal is distributed to all SDRAMs via a zero delay PLL driver. Note that the PLL must be given enough clock cycles to stabilize before any operation can be given (minimum stabilization time equal to 1 ms).
Absolute Maximum Ratings*: Item
Supply voltage (VCC Relative to VSS) Input/Output Voltage Operating temperature Storage temperature Short circuit output current
Symbol
VCC VI/O Topr Tstg Iout
Rating
-1.0 to +4.6 -1.0 to +4.6 0 to +70 -55 to +125 ±50
Unit
V V °C °C mA
* Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation should be restricted to the conditions as detailed in the sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions:
(Voltage referenced to VCC. TA = 0 to 70 °C)
Item
Supply voltage Input high voltage Input low voltage Operating Temperature
Symbol
VCC VIH VIL TA
Min.
3.0 2.0 -0.3 0
Typ.
3.3 +25
Max.
3.6 VCC+0.3 0.8 +70
Unit
V V V °C
Capacitance:
(TA=25°C, Vcc=3.3V±0.3V)
Parameter Input capacitance (Address/ WE, CKE0, /CAS, /CS0~/CS3) Input capacitance (/DQMBs) Input capacitance (CK0) Input capacitance (/RAS) Input/Output capacitance (DQ0~DQ63, CB0~CB7)
Symbol CIN CIN CIN CIN CI/O
Max. 10 5 4 20 13
Unit pF pF pF pF pF
Kentron Technologies, Inc. (978) 988-9100 Rev. 03/02
Page 2
128M X 72 REGISTERED SDRAM DIMM
Pin Names:
CK0-CK3 CKE0, CKE1 RAS* CAS* WE* CS0*-CS3* A0-A11 BA0, BA1 REGE NC or DU Clock Inputs Clock Enables Row Address Strobe Column Address Strobe Write Enable Chip Select Address Inputs SDRAM Bank Select Register Enable No Connect DQ0-DQ63 CB0-CB7 DQMB0-DQMB7 VCC VSS SCL SDA SA0-SA2 WP Data Inputs/Outputs ECC Data Input/Output Data Mask Enables Power supply Ground Serial Clock Serial Data Input/Output Decode Input Write Protect for SPD
REGE is the Register Enable pin which permits the DIMM to operate in buffered mode (inputs re-driven asynchronously) and "registered" mode (signals re-driven to SDRAMs when clock rises, and held valid until next rising clock). To conform to this specification, motherboards must pull this pin to a high state ("registered mode").
SDRAM DIMM Pinout:
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Designation VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VCC DQ14 DQ15 CB0 CB1 VSS NC NC VCC WE* DQMB0 DQMB1 S0* DU VSS A0 A2 A4 A6 A8 A10/AP BA1 VCC VCC CK0 No. 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Designation VSS DU CS2 DQMB2 DQMB3 DU VCC NC NC CB2 CB3 Vss DQ16 DQ17 DQ18 DQ19 Vcc DQ20 NC NC CKE1 Vss DQ21 DQ22 DQ23 Vss DQ24 DQ25 DQ26 DQ27 Vcc DQ28 DQ29 DQ30 DQ31 Vss CK2 NC WP SDA SCL Vcc No. 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 Designation Vss DQ32 DQ33 DQ34 DQ35 Vcc DQ36 DQ37 DQ38 DQ39 DQ40 Vss DQ41 DQ42 DQ43 DQ44 DQ45 Vcc DQ46 DQ47 CB4 CB5 Vss NC NC Vcc CAS* DQMB4 DQMB5 CS1* RAS* Vss A1 A3 A5 A7 A9 BA0 A11 Vcc CK1 A12 No. 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Designation Vss CKE0 CS3* DQMB6 DQMB7 A13 Vcc NC NC CB6 CB7 Vss DQ48 DQ49 DQ50 DQ51 Vcc DQ52 NC NC REGE Vss DQ53 DQ54 DQ55 Vss DQ56 DQ57 DQ58 DQ59 Vcc DQ60 DQ61 DQ62 DQ63 Vss CK3 NC SA0 SA1 SA2 Vcc
Kentron Technologies, Inc. (978) 988-9100 Rev. 03/02
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