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Details, datasheet, quote on part number:KT1664SSN3U
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Datasheet text preview:
8M / 16M X 64 UNBUFFERED SDRAM SODIMM
SDRAM MODULE
64 MByte (16M x 64) SDRAM 128 MByte (16M x 64) SDRAM Unbuffered 144 Pin SODIMM LOW PROFILE (1.03 inch height)
General Description:
This memory module is a high performance 64 / 128 Megabyte Unbuffered synchronous dynamic RAM module organized as 8M / 16M x 64 in a 144 pin Small Outline Dual In-Line Memory Module (SODIMM) package. The module utilizes eight (8) 1Mx4X16 64MbitSDRAM / 2Mx4x16 128Mbit SDRAM devices in a TSOP II 400 mil package. A 256 Byte Serial EEPROM contains the module configuration information. The EEPROM can be configured to a customer's specifications. These modules offer substantial advances in SDRAM operating performance, including the ability to synchronously burst data at a high rate with automatic column-address generation, interleave between internal banks in order to hide precharge time, and the capability to randomly change column address on each clock cycle during burst.
Features:
High density: 64 MB (8M x 64) 128 MB (16M x 64) Cycle time: 6 ns (166/156 MHz) 7.5 ns (133 MHz) 10 ns (100 MHz) JEDEC Standard 144 Pin Unbuffered SDRAM SODIMM Pinout PC100, PC133 and PC156 Compliant Single power supply of 3.3V ± 10% Serial Presence Detect LVTTL Compatible I/O and Clock Unbuffered Control and Address Lines Optional On-board PLL Clock Driver Auto Precharge and Auto Refresh (64ms) Modes handled by SDRAM Devices Programmable Burst Type, Burst Length and CAS Latency of SDRAM Devices Internal Pipeline Operation Fully Synchronous all signals registered on positive edge of system clock Package Height: 1.03 inches (+/- 10mils) Patented
Kentron Technologies, Inc. 155 West Street Wilmington, MA 01887 Phone: 978/988-9100 Fax 978/988-5550 www.kentrontech.com
8M / 16M X 64 UNBUFFERED SDRAM SODIMM
Operating Features:
The SDRAM SODIMM utilizes a clock input for the synchronization. Each operation of the SDRAM is determined by commands and all operations are referenced to a positive clock edge. CAS Latency defines the delay from when a Read Command is registered on a rising clock edge to when the data from the Read Command becomes available at the outputs. The CAS latency is expressed in terms of clock cycles. This specific DIMM supports 3 and 2 clock cycles. The burst mode is a very high-speed access mode utilizing an internal column address generator. Once a column address for the first access is set, following addresses are automatically generated by the internal column address counter. All control and address signals are supplied from the chipset through an unbuffered path to the SDRAMs. There are two clock signals supplied by the motherboard to synchronize the SODIMM. In the PLL option, the clock signal is fed from one clock only and distributed to all SDRAMs via a zero delay PLL driver. Note that the PLL must be given enough clock cycles to stabilize before any operation can be given (minimum stabilization time equal to 1 ms).
Absolute Maximum Ratings*: Item
Supply voltage (VCC Relative to VSS) Input/Output Voltage Operating temperature Storage temperature Short circuit output current
Symbol
VCC VI/O Topr Tstg Iout
Rating
-1.0 to +4.6 -1.0 to +4.6 0 to +70 -55 to +125 ±50
Unit
V V °C °C MA
* Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation should be restricted to the conditions as detailed in the sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions:
(Voltage referenced to VCC. TA = 0 to 70 °C)
Item
Supply voltage Input high voltage Input low voltage Operating Temperature
Symbol
VDD VIH VIL TA
Min.
3.1 2.0 -0.3 0
Typ.
3.3 +25
Max.
3.5 VDD+0.3 0.8 +70
Unit
V V V °C
Kentron Technologies, Inc. (978) 988-9100 Rev. 8/99
Page 2
8M / 16M X 64 UNBUFFERED SDRAM SODIMM
Capacitance:
(TA=25°C, Vcc=3.3V±0.3V)
Parameter Input capacitance (Address, /WE, /RAS, /CAS,) Input capacitance ( /CS0~/CS1, CKE0, CKE1) Input capacitance (/DQMBs) Input capacitance (CK0, CK1) Input capacitance (/RAS) Input/Output capacitance (DQ0~DQ63, CB0~CB7)
Symbol CIN CIN CIN CIN CIN CI/O
Max. 43 22 10 43 43 13
Unit pF pF pF pF pF pF
Pin Names:
CK0-CK3 CKE0 /RAS /CAS /WE /CS0-/CS3 A0-A11 BA0, BA1 NC or DU Clock Inputs Clock Enables Row Address Strobe Column Address Strobe Write Enable Chip Select Address Inputs SDRAM Bank Select No Connect DQ0-DQ63 CB0-CB7 /DQMB0-/DQMB7 VDD VSS SCL SDA SA0-SA2 WP Data Inputs/Outputs ECC Data Input/Output Data Mask Enables Power supply Ground Serial Clock Serial Data Input/Output Decode Input Write Protect for SPD
Kentron Technologies, Inc. (978) 988-9100 Rev. 8/99
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