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Details, datasheet, quote on part number:KT1672SSN3R
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Datasheet text preview:
16M X 72 LOW PROFILE REGISTERED SDRAM DIMM
SDRAM MODULE
128 MByte (16M x 72) SDRAM Low Profile Registered 168 Pin DIMM
General Description:
This memory module is a high performance 128 Megabyte Registered synchronous dynamic RAM module organized in one Bank as 16M x 72 in a 168 pin Low Dual In-Line Memory Module (DIMM) package. The module utilizes eighteen (18) 4Mx4X4 SDRAM (64ms Refresh) devices in a TSOP II 400 mil package. A 256 Byte Serial EEPROM contains the module configuration information. The EEPROM can be configured to Jedec specifications. These modules offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high rate with automatic column-address generation, interleave between internal banks in order to hide precharge time, and the capability to randomly change column address on each clock cycle during burst.
Features:
High density: Cycle time: 128 MB (16M x 72) 7.5ns (133 MHz) 10ns (100 MHz) JEDEC Standard 168 Pin Registered SDRAM DIMM PC-100/133 Compliant Single power supply of 3.3V ± 10% Serial Presence Detect LVTTL Compatible I/O and Clock Registered Control & Address Lines On-board PLL Clock Driver Refresh Rate 15.6usec Auto Precharge and Auto Refresh Modes handled by SDRAM Devices Programmable Burst Type, Burst Length and CAS Latency of SDRAM devices Internal Pipeline Operation Fully Synchronous all signals registered on positive edge of system clock Package Height: 1.20 inches
Kentron Technologies, Inc. 155 West Street Wilmington, MA 01887 Phone: (978) 988-9100 Fax (978) 988-5550 www.kentrontech.com
16M X 72 LOW PROFILE REGISTERED SDRAM DIMM
Operating Features:
The SDRAM DIMM utilizes a clock input for the synchronization. Each operation of the SDRAM is determined by commands and all operations are referenced to a positive clock edge. CAS Latency defines the delay from when a Read Command is registered on a rising clock edge to when the data from the Read Command becomes available at the outputs. The CAS latency is expressed in terms of clock cycles. This specific DIMM supports 3 and 2 clock cycles. The burst mode is a very high-speed access mode utilizing an internal column address generator. Once a column address for the first access is set, following addresses are automatically generated by the internal column address counter. All control and address signals are registered on-board and hence delayed by one cycle in arriving at the SDRAMs. The clock signal is distributed to all SDRAMs via a zero delay PLL driver. Note that the PLL must be given enough clock cycles to stabilize before any operation can be given (minimum stabilization time equal to 1 ms).
Absolute Maximum Ratings*: Item
Supply voltage (VCC Relative to VSS) Input/Output Voltage Operating temperature Storage temperature Short circuit output current
Symbol
VCC VI/O Topr Tstg Iout
Rating
-1.0 to +4.6 -1.0 to +4.6 0 to +70 -55 to +125 ±50
Unit
V V °C °C mA
* Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation should be restricted to the conditions as detailed in the sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions:
(Voltage referenced to VCC. TA = 0 to 70 °C)
Item
Supply voltage Input high voltage Input low voltage Operating Temperature
Symbol
VCC VIH VIL TA
Min.
3.0 2.0 -0.3 0
Typ.
3.3 +25
Max.
3.6 VCC+0.3 0.8 +70
Unit
V V V °C
Kentron Technologies, Inc. (978) 988-9100 Rev. 1.0 (6/00)
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16M X 72 LOW PROFILE REGISTERED SDRAM DIMM
Capacitance:
(TA=25°C, Vcc=3.3V±0.3V)
Parameter1 Input capacitance (Address/ WE, CKE0, /CAS) Input capacitance (/DQMBs, /CS0~/CS3) Input capacitance (CK0)2 Input capacitance (/RAS) Input/Output capacitance (DQ0~DQ63, CB0~CB7) 3
Symbol CIN CIN CIN CIN CI/O
Typ. 5.5 5.5 3.5 5.5 5.0
Unit pF pF pF pF pF
DC Characteristics:
(VCC = 3.3V±.3V, VSS=0V, TA=0 to + 70°C) Parameter
4
Symbol
133MHz Max. 2500 38 546 36 360 2460 3700 36
100MHz Max. 2450 38 546 36 360 2360 3700 36
Unit
Operating current (No Burst, TCK=min. TRC=min.) Precharge Standby Current (CKE=VIL, TCK = min. Bank idle) (CKE=VIH, TCK = min. Bank idle) Active Standby Current (CKE=VIL, TCK = min. ) (CKE=VIH, TCK = min. ) Burst Mode Current (tCK=min.) Refresh Current (per DIMM) (tCK=min., tRC=min., tRRD=min., Auto Refresh) Self Refresh Current (CKE=VIL)
ICC1 ICC2 ICC3 ICC4 ICC5 ICC6
mA mA
mA mA mA mA
Pin Names:
CK0-CK3 CKE0 /RAS /CAS /WE /CS0-/CS3 A0-A11 BA0, BA1 REGE NC or DU Clock Inputs Clock Enables Row Address Strobe Column Address Strobe Write Enable Chip Select Address Inputs SDRAM Bank Select Register Enable No Connect DQ0-DQ63 CB0-CB7 DQMB0-DQMB7 VCC VSS SCL SDA SA0-SA2 WP Data Inputs/Outputs ECC Data Input/Output Data Mask Enables Power supply Ground Serial Clock Serial Data Input/Output Decode Input Write Protect for SPD
REGE is the Register Enable pin which permits the DIMM to operate in buffered mode (inputs re-driven asynchronously) and "registered" mode (signals re-driven to SDRAMs when clock rises, and held valid until next rising clock). To conform to this specification, motherboards must pull this pin to a high state ("registered mode").
Based on Pericom ALVC16334 Register unless otherwise stated Pericom PI6C2510-133 PLL 3 Capacitance varies with by DRAM vendor 4 Typical Actual values run lower than Max Spec'ed Values.
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Kentron Technologies, Inc. (978) 988-9100 Rev. 1.0 (6/00)
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