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Details, datasheet, quote on part number:KT3272DSN
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Datasheet text preview:
32M X 72 REGISTERED DDR DIMM
SDRAM DDR MODULE
256 MByte (32M x 72) DDR SDRAM Registered 184 Pin DIMM Preliminary
General Description:
This memory module is a high performance 256 Megabyte Registered synchronous dynamic RAM module organized as 32M x 72 in a 184 pin Dual In-Line Memory Module (DIMM) package. The module utilizes eighteen (18) 16Mx8 DDR SDRAM devices in a TSOP II 400 mil package. A 256 Byte Serial EEPROM contains the module configuration information. The EEPROM can be configured to Jedec specifications. These modules offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high rate with automatic column-address generation, interleave between internal banks in order to hide precharge time, and the capability to randomly change column address on each clock cycle during burst.
Features:
High density: Cycle time: 256 MB (32M x 72) in two Banks 7.5ns (133 MHz) 10ns (100 MHz) Data Rate: 266Mbit/sec/pin (133 MHz) 200Mbit/sec/pin (100 MHz) CAS Latency: 2 (100MHz) 2, 2.5 (133MHz) JEDEC Standard 184 Pin Registered SDRAM DDR DIMM PC1600/2100 Compliant Single power supply of 2.5V ± 10% Serial Presence Detect SSTL2 Compatible I/O and Clock SSTL2 Registered Control & Address Lines On-board Differential PLL Clock Driver Refresh Rate 15.6uSec Auto Precharge and Auto Refresh Modes handled by SDRAM Devices Programmable Burst Type, Burst Length and CAS Latency of SDRAM devices Internal Pipeline Operation Fully Synchronous all signals registered on positive edge of system clock Data provided during Reads and Writes at twice the clock frequency Package Height: 1.20 inches
Kentron Technologies, Inc. 155 West Street Wilmington, MA 01887 Phone: (978) 988-9100 Fax (978) 988-5550 www.kentrontech.com
32M X 72 REGISTERED DDR DIMM
Operating Features:
The SDRAM DDR DIMM utilizes a clock input for the synchronization. Each operation of the SDRAM is determined by commands and all operations are referenced to a positive clock edge. CAS Latency defines the delay from when a Read Command is registered on a rising clock edge to when the data from the Read Command becomes available at the outputs. The CAS latency is expressed in terms of clock cycles. This specific DIMM supports 2.5 and 2 clock cycles. The burst mode is a very high-speed access mode utilizing an internal column address generator. Once a column address for the first access is set, following addresses are automatically generated by the internal column address counter. All control and address signals are registered on-board and hence delayed by one cycle in arriving at the SDRAMs. The clock signal is distributed to all SDRAMs via a zero delay PLL driver. Note that the PLL must be given enough clock cycles to stabilize before any operation can be given (minimum stabilization time equal to 1 ms).
Absolute Maximum Ratings*: Item
VDD Supply voltage Relative to VSS VDDQ Supply voltage Relative to VSS VREF and Inputs Relative to VSS I/O Voltage Relative to VSS Operating temperature Storage temperature Short circuit output current
Symbol
VDD VDDQ VREF, VIN VI/O Topr Tstg Iout
Rating
-1V to +3.6V -1V to +3.6V -1V to +3.6V -0.5V to VDD +0.5V 0 to +70 -55 to +150 50
Unit
V V V V °C °C mA
* Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation should be restricted to the conditions as detailed in the sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Kentron Technologies, Inc. (978) 988-9100 Rev. 03/02
Page 2
32M X 72 REGISTERED DDR DIMM
Recommended Operating Conditions:
(Voltage referenced to VSS =0V ,TA = 0 to 70 °C)
Item
Supply voltage I/O Supply voltage I/O Reference Voltage I/O Termination Voltage Input high Voltage Input low Voltage Clock Input Voltage Clock Differential Voltage Clock Crossing Point Voltage Input and Output Leakage Output High and Low Currents
Symbol
VDD VDDQ VREF VTT VIH VIL VIN VID VIX II , IOZ IOH , IOL
Min.
2.3 2.3 0.49x VDD VREF -0.04 VREF +0.18 -0.3 -0.3 0.36 1.15 -5 -16.8 , +16.8
Typ.
2.5 2.5 1.25 VREF -
Max.
2.7 2.7 0.51x VDD VREF +0.04 VDD +0.3 VREF -0.18 VDDQ +0.3 VDDQ +0.6 1.35 5 -
Unit
V V V V V V V V V uA mA
Capacitance:
(TA=25°C, Vcc=2.5V±0.2V)
Parameter Input capacitance (CK, CK\) Input/Output capacitance (DQs, DQSs, DMs,CBs) Input capacitance (All other input-only pins)
Symbol CI1 CIO CI2
Max. 3 13 4
Unit PF PF PF
Kentron Technologies, Inc. (978) 988-9100 Rev. 03/02
Page 3
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