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Details, datasheet, quote on part number:KT3272SFN0U-XXB
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Datasheet text preview:
32MX 72 UNBUFFERED FEMMA SDRAM SODIMM
SDRAM FEMMA SODIMM MODULE
256 MByte (32M x 72) SDRAM Unbuffered ECC 144 Pin SODIMM
General Description:
This memory module is a high density 256 Megabyte Unbuffered synchronous dynamic RAM module organized as 32M x 72 in a 144-pin ECC Small Outline Dual In-Line Memory Module (SODIMM) package. The module utilizes eighteen (18) 4Mx4X8 128Mbit SDRAM devices in a TSOP II 400 mil package. A zero delay buffer drives the input clock to all SDRAM devices. A 256 Byte Serial EEPROM contains the module configuration information. The EEPROM can be configured to a customer's specifications. These modules offer substantial advances in SDRAM operating performance, including the ability to synchronously burst data at a high rate with automatic column-address generation, interleave between internal banks in order to hide precharge time, and the capability to randomly change column address on each clock cycle during burst.
Features:
High density: Cycle time: 256 MB (32M x 72) 10 ns (100 MHz) 7.5 ns (133 MHz) JEDEC Standard 144 Pin Unbuffered SDRAM SODIMM Pinout PC133 and PC100 Compliant Single power supply of 3.3V ± 10% Serial Presence Detect LVTTL Compatible I/O and Clock Unbuffered Control and Address Lines ECC operation On-board PLL Clock Driver (2 msec settling time) 4K Refresh in 64ms (15.6 usec per row) Auto Precharge and Auto Refresh Modes handled by SDRAM Devices Programmable Burst Type, Burst Length and CAS Latency of SDRAM Devices Internal Pipeline Operation Fully Synchronous all signals registered on positive edge of system clock Package Height: 1.25 inches (+/- 10mils) Patented
Kentron Technologies, Inc. 155 West Street Wilmington, MA 01887 Phone: (978) 988-9100 Fax (978) 988-5550 www.kentrontech.com
32M X 72 UNBUFFERED FEMMA SDRAM SODIMM
Operating Features:
The FEMMA SDRAM SODIMM utilizes a clock input for the synchronization. Each operation of the SDRAM is determined by commands and all operations are referenced to a positive clock edge. CAS Latency defines the delay from when a Read Command is registered on a rising clock edge to when the data from the Read Command becomes available at the outputs. The CAS latency is expressed in terms of clock cycles. This specific DIMM supports 3 and 2 clock cycles. The burst mode is a very high-speed access mode utilizing an internal column address generator. Once a column address for the first access is set, following addresses are automatically generated by the internal column address counter. All control and address signals are supplied from the chipset through an unbuffered path to the SDRAMs. CK0 supplied by the motherboard feeds into a Phase Lock Loop (PLL) on the module to drive all sixteen SDRAMs.
Kentron Technologies, Inc. (978) 988-9100 Rev. 12/01
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32M X 72 UNBUFFERED FEMMA SDRAM SODIMM
Absolute Maximum Ratings*: Item
Supply voltage (VCC Relative to VSS) Input/Output Voltage Operating temperature Storage temperature Short circuit output current
Symbol
VCC VI/O Topr Tstg Iout
Rating
-1.0 to +4.6 -1.0 to +4.6 0 to +70 -55 to +125 ±50
Unit
V V °C °C mA
* Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation should be restricted to the conditions as detailed in the sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions:
(Voltage referenced to VCC. TA = 0 to 70 °C)
Item
Supply voltage Input high voltage Input low voltage Operating Temperature
Symbol
VDD VIH VIL TA
Min.
3.1 2.0 -0.3 0
Typ.
3.3 +25
Max.
3.5 VDD+0.3 0.8 +70
Unit
V V V °C
Capacitance:
(TA=25°C, Vcc=3.3V±0.3V)
Parameter Input capacitance (Address, /WE, CKE0,1 , /CAS) Input capacitance ( /CS0~/CS1) Input capacitance (/DQMBs) Input capacitance (CK0) Input capacitance (/RAS) Input/Output capacitance (DQ0~DQ63, CB0~CB7)
Symbol CIN CIN CIN CIN CIN CI/O
Max. 88 29 15 5 88 18
Unit pF pF pF pF pF pF
Kentron Technologies, Inc. (978) 988-9100 Rev. 12/01
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